Line data Source code
1 : #ifndef DTC_REGISTERS_H
2 : #define DTC_REGISTERS_H
3 :
4 : #include <bitset> // std::bitset
5 : // #include <cstdint> // uint8_t, uint16_t
6 : #include <functional> // std::bind, std::function
7 : #include <vector> // std::vector
8 :
9 : #include "CFOandDTC_Registers.h"
10 : #include "artdaq-core-mu2e/Overlays/DTC_Types/DTC_EVBStatsType.h"
11 :
12 : namespace DTCLib
13 : {
14 : enum DTC_Register : uint16_t
15 : {
16 : DTCLIB_COMMON_REGISTERS, // Moved here all registers in common with CFO
17 :
18 : DTC_Register_ROCEmulationEnable = 0x9110,
19 :
20 : // 0x913C Reserved
21 : DTC_Register_SERDES_RXCDRLockStatus = 0x9140,
22 : DTC_Register_DMATimeoutPreset = 0x9144,
23 : DTC_Register_ROCReplyTimeout = 0x9148,
24 : DTC_Register_ROCReplyTimeoutError = 0x914C,
25 : // 0x9150 Reserved
26 : DTC_Register_EVBPartitionID = 0x9154,
27 : DTC_Register_EVBConfiguration = 0x9158,
28 : DTC_Register_EVBPacketControl = 0x915C,
29 : DTC_Register_EVBStats = 0x9160,
30 : DTC_Register_SERDESClock_IICBusControl = 0x9164,
31 : DTC_Register_EVBIdleBurst = 0x9170,
32 : DTC_Register_EVBResendCount = 0x9174, // [31:16] resends served by TX, [15:0] requested by RX
33 : DTC_Register_EVBLocalChunkCap = 0x9178, // [15:0] longest self chunk in 8-byte words; reset 0x0400, 0 = whole-record chunks, 1..31 act as 32
34 : DTC_Register_EVBRemoteChunkControl = 0x917C, // build 3 (hw agent 2026-10-07): [31:16] hold clocks, [15:0] minimum remote chunk words; reset 0x0400_0080
35 : DTC_Register_EVBRxIllegalDestCount = 0x9180, // hw agent 2026-10-13: [15:0] 10GbE RX frames whose dest MAC was not ours (non-broadcast); switch flooding; saturates 0xFFFF, SoftReset clear
36 : DTC_Register_CFOEmulation_LoopbackDelayMeasure = 0x9184,
37 : // Reserved - formerly... DTC_Register_DataPendingTimer = 0x9188,
38 : // 0x918C Reserved
39 : DTC_Register_FIFOFullErrorFlag0 = 0x9190,
40 : DTC_Register_FIFOFullErrorFlag1 = 0x9194,
41 : DTC_Register_FIFOFullErrorFlag2 = 0x9198,
42 : DTC_Register_ReceivePacketError = 0x919C,
43 : DTC_Register_CFOEmulation_TimestampLow = 0x91A0,
44 : DTC_Register_CFOEmulation_TimestampHigh = 0x91A4,
45 : DTC_Register_CFOEmulation_HeartbeatInterval = 0x91A8,
46 : DTC_Register_CFOEmulation_NumHeartbeats = 0x91AC,
47 : DTC_Register_ROCEmulation_NumPacketsLinks10 = 0x91B0,
48 : DTC_Register_ROCEmulation_NumPacketsLinks32 = 0x91B4,
49 : DTC_Register_ROCEmulation_NumPacketsLinks54 = 0x91B8,
50 : DTC_Register_CFOEmulation_NumNullHeartbeats = 0x91BC,
51 : DTC_Register_CFOEmulation_EventMode1 = 0x91C0,
52 : DTC_Register_CFOEmulation_EventMode2 = 0x91C4,
53 : DTC_Register_CFOEventModeRequiredMask = 0x91C8,
54 : DTC_Register_RXPacketCountErrorFlags = 0x91CC,
55 : DTC_Register_DetEmulation_DMACount = 0x91D0,
56 : DTC_Register_DetEmulation_DelayCount = 0x91D4,
57 : DTC_Register_DetEmulation_Control0 = 0x91D8,
58 : DTC_Register_DetEmulation_Control1 = 0x91DC,
59 : DTC_Register_DetEmulation_DataStartAddress = 0x91E0,
60 : DTC_Register_DetEmulation_DataEndAddress = 0x91E4,
61 : DTC_Register_EthernetFramePayloadSize = 0x91EC,
62 : DTC_Register_CFOEmulation_DataRequestDelay = 0x91E8,
63 : DTC_Register_EthernetFrameMaxPayload = 0x91EC,
64 : DTC_Register_EVBTxHistoryRead = 0x91F0, // hw agent 2026-10-13: TX packet history readback, one entry per read, auto-advance, 0xFFFFFFFF past the end
65 : DTC_Register_CFOEmulation_40MHzClockMarkerInterval = 0x91F4,
66 : DTC_Register_CFOMarkerEnables = 0x91F8,
67 : DTC_Register_ROCFinishThreshold = 0x91FC,
68 : DTC_Register_EVBHighLevelCounters0 = 0x9200, // [31:16] Self-transfer words, [15:0] ROC input words
69 : DTC_Register_EVBHighLevelCounters1 = 0x9204, // [31:16] DDR->TX words, [15:0] DDR FIFO write words
70 : DTC_Register_EVBHighLevelCounters2 = 0x9208, // [31:16] DMA output words, [15:0] Buffer manager output words
71 : DTC_Register_EVBHighLevelCounters3 = 0x920C, // [15:0] GBE RX words
72 : // EVB3 stall-time counters (hw agent 2026-10-06, status doc A2): 32-bit counts of user_clk clocks
73 : // (4 ns) the condition was true since SoftReset, wrap at 2^32 (~17 s); divide by 0x9228 for a duty ratio
74 : DTC_Register_EVBStallTXCredit = 0x9210, // TX idle with words but no RX credit (0x9370 bit 18)
75 : DTC_Register_EVBStallTXWire = 0x9214, // a frame on the 10GbE wire
76 : DTC_Register_EVBStallBufferManagerLocal = 0x9218, // buffer manager streaming a self chunk to DMA
77 : DTC_Register_EVBStallBufferManagerRemoteWait = 0x921C, // a remote source FIFO held words while no remote chunk was served
78 : DTC_Register_EVBStallDDRRead = 0x9220, // a DDR read burst in flight on the TX side
79 : DTC_Register_EVBStallROCHeld = 0x9224, // ROC input valid and not ready (0x9370 bit 16)
80 : DTC_Register_EVBStallTimebase = 0x9228, // clocks since SoftReset (denominator)
81 : // build after 0xe6100696 (hw agent 2026-10-07): ROC-held time split four ways; the four must add up to 0x9224
82 : DTC_Register_EVBStallROCHeldPart1 = 0x922C,
83 : DTC_Register_EVBStallROCHeldPart2 = 0x9230,
84 : DTC_Register_EVBStallROCHeldPart3 = 0x9234,
85 : DTC_Register_EVBStallROCHeldPart4 = 0x9238,
86 : DTC_Register_EVBStallShare5 = 0x923C, // DDR write busy (hw agent 2026-10-08)
87 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link3 = 0x922C,
88 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link4 = 0x9230,
89 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link5 = 0x9234,
90 : // Reserved - formerly... DTC_Register_ReceivePacketCount_CFOLink = 0x9238,
91 : // 0x923C Reserved
92 : // EVB3 output stage (build after 0xd6100794, hw agent 2026-10-07): registered copies of the handshake
93 : // into the PCIe engine; 0x9240/0x9228 is the exact share behind polled 0x9370 bit 23
94 : DTC_Register_EVBOutputHoldClocks = 0x9240, // clocks the output held a word the PCIe engine would not take
95 : DTC_Register_EVBOutputLongestHold = 0x9244, // longest single hold since SoftReset, 4 ns clocks (>= 65536 = a 262 us hold)
96 : DTC_Register_EVBOutputWordsAccepted = 0x9248, // words the engine accepted; rate = delta x 8 B / (delta 0x9228 x 4 ns)
97 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link3 = 0x924C,
98 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link4 = 0x9250,
99 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link5 = 0x9254,
100 : // Reserved - formerly... DTC_Register_TransmitByteCount_CFOLink = 0x9258,
101 : DTC_Register_EVBTxHistoryStatus = 0x925C, // hw agent 2026-10-13: [31] frozen, [30:26] first resend dest, [25:18] peer last ack seq, [9:0] entries written
102 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link0 = 0x9260,
103 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link1 = 0x9264,
104 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link2 = 0x9268,
105 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link3 = 0x926C,
106 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link4 = 0x9270,
107 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link5 = 0x9274,
108 : // Reserved - formerly... DTC_Register_TransmitPacketCount_CFOLink = 0x9278,
109 : // 0x927C Reserved
110 : // 0x9280 Reserved
111 : // 0x9290 Reserved
112 : // 0x92A0 Reserved
113 : DTC_Register_TXPRBSControl = 0x92B0,
114 : DTC_Register_RXPRBSControl = 0x92B4,
115 : // 0x92B8 Reserved
116 : // 0x92BC Reserved
117 : DTC_Register_EventModeLookupTableControl = 0x92C0,
118 : // 0x92C4-0x92EC Reserved
119 : DTC_Register_DD3TestRegister = 0x92F0,
120 : // 0x92F4 Reserved
121 : // 0x92F8 Reserved
122 : // 0x92FC Reserved
123 : DTC_Register_SERDESTXRXInvertEnable = 0x9300,
124 : // 0x9304 Reserved
125 : DTC_Register_JitterAttenuatorCSR = 0x9308,
126 : // 0x930C Reserved
127 : // 0x9310 Reserved
128 : DTC_Register_SFP_IICBusControl = 0x9314,
129 : DTC_Register_SFP_IICBusLow = 0x9318,
130 : DTC_Register_SFP_IICBusHigh = 0x931C,
131 : DTC_Register_RetransmitRequestCount_Link0 = 0x9320,
132 : DTC_Register_RetransmitRequestCount_Link1 = 0x9324,
133 : DTC_Register_RetransmitRequestCount_Link2 = 0x9328,
134 : DTC_Register_RetransmitRequestCount_Link3 = 0x932C,
135 : DTC_Register_RetransmitRequestCount_Link4 = 0x9330,
136 : DTC_Register_RetransmitRequestCount_Link5 = 0x9334,
137 : // 0x9338 Reserved
138 : // 0x933C Reserved
139 : DTC_Register_MissedCFOPacketCount_Link0 = 0x9340,
140 : DTC_Register_MissedCFOPacketCount_Link1 = 0x9344,
141 : DTC_Register_MissedCFOPacketCount_Link2 = 0x9348,
142 : DTC_Register_MissedCFOPacketCount_Link3 = 0x934C,
143 : DTC_Register_MissedCFOPacketCount_Link4 = 0x9350,
144 : DTC_Register_MissedCFOPacketCount_Link5 = 0x9354,
145 : // 0x9358 Reserved
146 : // 0x935C Reserved
147 : DTC_Register_LocalFragmentDropCount = 0x9360,
148 : DTC_Register_EVBSubEventReceiveTimerPreset = 0x9364,
149 : DTC_Register_EVBSERDESPRBSControlStatus = 0x9368,
150 : // 0x936C Reserved
151 : DTC_Register_EventBuilderErrorFlags = 0x9370,
152 : DTC_Register_InputBufferErrorFlags = 0x9374,
153 : DTC_Register_OutputBufferErrorFlags = 0x9378,
154 : DTC_Register_Link0ErrorFlags = 0x9380,
155 : DTC_Register_Link1ErrorFlags = 0x9384,
156 : DTC_Register_Link2ErrorFlags = 0x9388,
157 : DTC_Register_Link3ErrorFlags = 0x938C,
158 : DTC_Register_Link4ErrorFlags = 0x9390,
159 : DTC_Register_Link5ErrorFlags = 0x9394,
160 : DTC_Register_CFOLinkErrorFlags = 0x9398,
161 : DTC_Register_LinkMuxErrorFlags = 0x939C,
162 : DTC_Register_SFPControlStatus = 0x93A4,
163 : // 0x93A8 Reserved
164 : // 0x93AC Reserved
165 : DTC_Register_RXCDRUnlockCount_Link0 = 0x93B0,
166 : DTC_Register_RXCDRUnlockCount_Link1 = 0x93B4,
167 : DTC_Register_RXCDRUnlockCount_Link2 = 0x93B8,
168 : DTC_Register_RXCDRUnlockCount_Link3 = 0x93BC,
169 : DTC_Register_RXCDRUnlockCount_Link4 = 0x93C0,
170 : DTC_Register_RXCDRUnlockCount_Link5 = 0x93C4,
171 : DTC_Register_RXCDRUnlockCount_CFOLink = 0x93C8,
172 : DTC_Register_JitterAttenuatorLossOfLockCount = 0x93CC,
173 : DTC_Register_CFOLinkEventStartErrorCount = 0x93D0,
174 : DTC_Register_CFOLink40MHzErrorCount = 0x93D4,
175 : DTC_Register_InputBufferDropCount = 0x93D8,
176 : DTC_Register_OutputBufferDropCount = 0x93DC,
177 : DTC_Register_RTFHistIdelay = 0x93E0,
178 : // 0x93E4 - 0x93F4 Reserved
179 : DTC_Register_DataRequest_Low = 0x93F8,
180 : DTC_Register_DataRequest_High = 0x93FC,
181 : DTC_Register_FPGAProgramData = 0x9400,
182 : DTC_Register_FPGAPROMProgramStatus = 0x9404,
183 : DTC_Register_FPGACoreAccess = 0x9408,
184 : // 0x940C Reserved
185 : DTC_Register_SlowOpticalLinksDiag = 0x9410,
186 : DTC_Register_DiagSERDESErrorEnable = 0x9414,
187 : DTC_Register_DiagSERDESPacket0 = 0x9418,
188 : DTC_Register_DiagSERDESPacket1 = 0x941C,
189 : DTC_Register_DiagSERDESPacket2 = 0x9420,
190 : DTC_Register_DiagSERDESPacket3 = 0x9424,
191 : DTC_Register_DiagSERDESPacket4 = 0x9428,
192 : DTC_Register_DiagSERDESPacket5 = 0x942C,
193 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags0 = 0x9430,
194 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags1 = 0x9434,
195 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags2 = 0x9438,
196 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags3 = 0x943C,
197 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags0 = 0x9440,
198 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags1 = 0x9444,
199 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags2 = 0x9448,
200 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags3 = 0x944C,
201 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags0 = 0x9450,
202 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags1 = 0x9454,
203 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags2 = 0x9458,
204 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags3 = 0x945C,
205 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags0 = 0x9460,
206 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags1 = 0x9464,
207 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags2 = 0x9468,
208 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags3 = 0x946C,
209 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags0 = 0x9470,
210 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags1 = 0x9474,
211 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags2 = 0x9478,
212 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags3 = 0x947C,
213 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags0 = 0x9480,
214 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags1 = 0x9484,
215 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags2 = 0x9488,
216 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags3 = 0x948C,
217 : DTC_Register_DataPendingDiagTimer_Link0 = 0x9490,
218 : DTC_Register_DataPendingDiagTimer_Link1 = 0x9494,
219 : DTC_Register_DataPendingDiagTimer_Link2 = 0x9498,
220 : DTC_Register_DataPendingDiagTimer_Link3 = 0x949C,
221 : DTC_Register_DataPendingDiagTimer_Link4 = 0x94A0,
222 : DTC_Register_DataPendingDiagTimer_Link5 = 0x94A4,
223 : // 0x94A8 Reserved
224 : // 0x94AC Reserved
225 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link0 = 0x94B0,
226 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link1 = 0x94B4,
227 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link2 = 0x94B8,
228 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link3 = 0x94BC,
229 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link4 = 0x94C0,
230 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link5 = 0x94C4,
231 : // 0x94C8 Reserved
232 : // 0x94CC Reserved
233 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link0 = 0x94D0,
234 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link1 = 0x94D4,
235 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link2 = 0x94D8,
236 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link3 = 0x94DC,
237 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link4 = 0x94E0,
238 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link5 = 0x94E4,
239 : // 0x94E8 - 0x94FC Reserved
240 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link0 = 0x9500,
241 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link1 = 0x9504,
242 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link2 = 0x9508,
243 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link3 = 0x950C,
244 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link4 = 0x9510,
245 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link5 = 0x9514,
246 : DTC_Register_SERDES_CharacterNotInTableErrorCount_CFOLink = 0x9518,
247 : // 0x951C Reserved
248 : DTC_Register_SERDES_RXDisparityErrorCount_Link0 = 0x9520,
249 : DTC_Register_SERDES_RXDisparityErrorCount_Link1 = 0x9524,
250 : DTC_Register_SERDES_RXDisparityErrorCount_Link2 = 0x9528,
251 : DTC_Register_SERDES_RXDisparityErrorCount_Link3 = 0x952C,
252 : DTC_Register_SERDES_RXDisparityErrorCount_Link4 = 0x9530,
253 : DTC_Register_SERDES_RXDisparityErrorCount_Link5 = 0x9534,
254 : DTC_Register_SERDES_RXDisparityErrorCount_CFOLink = 0x9538,
255 : // 0x953C Reserved
256 : DTC_Register_SERDES_RXPRBSErrorCount_Link0 = 0x9540,
257 : DTC_Register_SERDES_RXPRBSErrorCount_Link1 = 0x9544,
258 : DTC_Register_SERDES_RXPRBSErrorCount_Link2 = 0x9548,
259 : DTC_Register_SERDES_RXPRBSErrorCount_Link3 = 0x954C,
260 : DTC_Register_SERDES_RXPRBSErrorCount_Link4 = 0x9550,
261 : DTC_Register_SERDES_RXPRBSErrorCount_Link5 = 0x9554,
262 : DTC_Register_SERDES_RXPRBSErrorCount_CFOLink = 0x9558,
263 : // 0x955C Reserved
264 : DTC_Register_SERDES_RXCRCErrorCount_Link0 = 0x9560,
265 : DTC_Register_SERDES_RXCRCErrorCount_Link1 = 0x9564,
266 : DTC_Register_SERDES_RXCRCErrorCount_Link2 = 0x9568,
267 : DTC_Register_SERDES_RXCRCErrorCount_Link3 = 0x956C,
268 : DTC_Register_SERDES_RXCRCErrorCount_Link4 = 0x9570,
269 : DTC_Register_SERDES_RXCRCErrorCount_Link5 = 0x9574,
270 : DTC_Register_SERDES_RXCRCErrorCount_CFOLink = 0x9578,
271 : DTC_Register_SERDES_RXCRCErrorControl = 0x957C,
272 : // 0x9580 - 0x958C Reserved
273 : DTC_Register_EBVSERDES_RXPacketErrorCount = 0x9590,
274 : // 0x9594 - 0x959C Reserved
275 : DTC_Register_JitterAttenuator_SERDES_RXRecoveredClockLOSCount = 0x95A0,
276 : DTC_Register_JitterAttenuator_SERDES_RXExternalClockLOSCount = 0x95A4,
277 : // 0x9598 - 0x960C Reserved
278 : DTC_Register_ROCEmulator_InterpacketDelay_Link0 = 0x9610,
279 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link1 = 0x9614,
280 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link2 = 0x9618,
281 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link3 = 0x961C,
282 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link4 = 0x9620,
283 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link5 = 0x9624,
284 : // 0x9628 Reserved
285 : // 0x962C Reserved
286 : DTC_Register_TXDataRequestPacketCount_Link0 = 0x9630,
287 : DTC_Register_TXDataRequestPacketCount_Link1 = 0x9634,
288 : DTC_Register_TXDataRequestPacketCount_Link2 = 0x9638,
289 : DTC_Register_TXDataRequestPacketCount_Link3 = 0x963C,
290 : DTC_Register_TXDataRequestPacketCount_Link4 = 0x9640,
291 : DTC_Register_TXDataRequestPacketCount_Link5 = 0x9644,
292 : DTC_Register_CFOTXClockMarkerCount_Link6 = 0x9648,
293 : // 0x9648 Reserved
294 : // 0x964C Reserved
295 : DTC_Register_TXHeartbeatPacketCount_Link0 = 0x9650,
296 : DTC_Register_TXHeartbeatPacketCount_Link1 = 0x9654,
297 : DTC_Register_TXHeartbeatPacketCount_Link2 = 0x9658,
298 : DTC_Register_TXHeartbeatPacketCount_Link3 = 0x965C,
299 : DTC_Register_TXHeartbeatPacketCount_Link4 = 0x9660,
300 : DTC_Register_TXHeartbeatPacketCount_Link5 = 0x9664,
301 : DTC_Register_CFOTXHeartbeatPacketCount_Link5 = 0x9668,
302 : // 0x9668 Reserved
303 : // 0x966C Reserved
304 : DTC_Register_RXDataHeaderPacketCount_Link0 = 0x9670,
305 : DTC_Register_RXDataHeaderPacketCount_Link1 = 0x9674,
306 : DTC_Register_RXDataHeaderPacketCount_Link2 = 0x9678,
307 : DTC_Register_RXDataHeaderPacketCount_Link3 = 0x967C,
308 : DTC_Register_RXDataHeaderPacketCount_Link4 = 0x9680,
309 : DTC_Register_RXDataHeaderPacketCount_Link5 = 0x9684,
310 : DTC_Register_CFOCDCDiag = 0x9688,
311 : // 0x968C Reserved
312 : DTC_Register_RXDataPacketCount_Link0 = 0x9690,
313 : DTC_Register_RXDataPacketCount_Link1 = 0x9694,
314 : DTC_Register_RXDataPacketCount_Link2 = 0x9698,
315 : DTC_Register_RXDataPacketCount_Link3 = 0x969C,
316 : DTC_Register_RXDataPacketCount_Link4 = 0x96A0,
317 : DTC_Register_RXDataPacketCount_Link5 = 0x96A4,
318 : // 0x96A8 Reserved
319 : // 0x96AC Reserved
320 : DTC_Register_EVBDiagnosticRXPacket_Low = 0x96B0,
321 : DTC_Register_EVBDiagnosticRXPacket_High = 0x96B4,
322 : DTC_Register_EventModeLookupTableStart = 0xA000,
323 : DTC_Register_EventModeLookupTableEnd = 0xA3FC,
324 :
325 : DTC_Register_RXDataDiagnosticFIFO_Link0 = 0x96D0,
326 : DTC_Register_RXDataDiagnosticFIFO_Link1 = 0x96D4,
327 : DTC_Register_RXDataDiagnosticFIFO_Link2 = 0x96D8,
328 : DTC_Register_RXDataDiagnosticFIFO_Link3 = 0x96DC,
329 : DTC_Register_RXDataDiagnosticFIFO_Link4 = 0x96E0,
330 : DTC_Register_RXDataDiagnosticFIFO_Link5 = 0x96E4,
331 :
332 : DTC_Register_TXDataDiagnosticFIFO_Link0 = 0x96E8,
333 : DTC_Register_TXDataDiagnosticFIFO_Link1 = 0x96EC,
334 : DTC_Register_TXDataDiagnosticFIFO_Link2 = 0x96F0,
335 : DTC_Register_TXDataDiagnosticFIFO_Link3 = 0x96F4,
336 : DTC_Register_TXDataDiagnosticFIFO_Link4 = 0x96F8,
337 : DTC_Register_TXDataDiagnosticFIFO_Link5 = 0x96FC,
338 :
339 : DTC_Register_RXDataDiagnosticFIFO_LinkCFO = 0x9700,
340 : DTC_Register_TXDataDiagnosticFIFO_LinkCFO = 0x9708,
341 :
342 : DTC_Register_TXEventWindowMarkerCount_Link0 = 0xA400,
343 : DTC_Register_TXEventWindowMarkerCount_Link1 = 0xA404,
344 : DTC_Register_TXEventWindowMarkerCount_Link2 = 0xA408,
345 : DTC_Register_TXEventWindowMarkerCount_Link3 = 0xA40C,
346 : DTC_Register_TXEventWindowMarkerCount_Link4 = 0xA410,
347 : DTC_Register_TXEventWindowMarkerCount_Link5 = 0xA414,
348 : DTC_Register_CFOTXEventWindowMarkerCount_Link6 = 0xA418,
349 :
350 : DTC_Register_ReceiveDHTimeoutCount_Link0 = 0xA420,
351 : DTC_Register_ReceiveDHTimeoutCount_Link1 = 0xA424,
352 : DTC_Register_ReceiveDHTimeoutCount_Link2 = 0xA428,
353 : DTC_Register_ReceiveDHTimeoutCount_Link3 = 0xA42C,
354 : DTC_Register_ReceiveDHTimeoutCount_Link4 = 0xA430,
355 : DTC_Register_ReceiveDHTimeoutCount_Link5 = 0xA434,
356 :
357 : DTC_Register_TXNullHeartbeatCount_Link0 = 0xA440,
358 : DTC_Register_TXNullHeartbeatCount_Link1 = 0xA444,
359 : DTC_Register_TXNullHeartbeatCount_Link2 = 0xA448,
360 : DTC_Register_TXNullHeartbeatCount_Link3 = 0xA44C,
361 : DTC_Register_TXNullHeartbeatCount_Link4 = 0xA450,
362 : DTC_Register_TXNullHeartbeatCount_Link5 = 0xA454,
363 :
364 : DTC_Register_TXBlockedHeartbeatCount_Link0 = 0xA460,
365 : DTC_Register_TXBlockedHeartbeatCount_Link1 = 0xA464,
366 : DTC_Register_TXBlockedHeartbeatCount_Link2 = 0xA468,
367 : DTC_Register_TXBlockedHeartbeatCount_Link3 = 0xA46C,
368 : DTC_Register_TXBlockedHeartbeatCount_Link4 = 0xA470,
369 : DTC_Register_TXBlockedHeartbeatCount_Link5 = 0xA474,
370 :
371 : DTC_Register_TXNonnullHeartbeatCount_Link0 = 0xA480,
372 : DTC_Register_TXNonnullHeartbeatCount_Link1 = 0xA484,
373 : DTC_Register_TXNonnullHeartbeatCount_Link2 = 0xA488,
374 : DTC_Register_TXNonnullHeartbeatCount_Link3 = 0xA48C,
375 : DTC_Register_TXNonnullHeartbeatCount_Link4 = 0xA490,
376 : DTC_Register_TXNonnullHeartbeatCount_Link5 = 0xA494,
377 :
378 : DTC_Register_Invalid,
379 : // };
380 : }; // end DTC_Register enum
381 :
382 : /// <summary>
383 : /// The DTC_Registers class represents the DTC Register space, and all the methods necessary to read and write those
384 : /// registers. Each register has, at the very least, a read method, a write method, and a RegisterFormatter method
385 : /// which formats the register value in a human-readable way.
386 : /// </summary>
387 : class DTC_Registers : public CFOandDTC_Registers
388 : {
389 : public:
390 : explicit DTC_Registers(DTC_SimMode mode, int dtc, std::string simFileName, unsigned linkMask = 0x1, std::string expectedDesignVersion = "", bool skipInit = false, const std::string& uid = "");
391 :
392 : virtual ~DTC_Registers();
393 :
394 : //
395 : // DTC Sim Mode Virtual Register
396 : //
397 : /// <summary>
398 : /// Get the current DTC_SimMode of this DTC_Registers object
399 : /// </summary>
400 : /// <returns></returns>
401 0 : DTC_SimMode GetSimMode() const { return simMode_; }
402 :
403 : DTC_SimMode SetSimMode(std::string expectedDesignVersion, DTC_SimMode mode, int dtc, std::string simMemoryFile, unsigned linkMask, bool skipInit = false, const std::string& uid = "");
404 :
405 : //
406 : // Register IO Functions
407 : //
408 :
409 : // Design Status Register
410 : bool ReadDDRInterfaceReset(std::optional<uint32_t> val = std::nullopt);
411 : void SetDDRInterfaceReset(bool reset);
412 : void ResetDDRInterface();
413 : bool ReadDDRAutoCalibrationDone(std::optional<uint32_t> val = std::nullopt);
414 : RegisterFormatter FormatDesignStatus();
415 :
416 : // DTC Control Register
417 : void EnableCFOEmulation(); // B30
418 : void DisableCFOEmulation(); // B30
419 : bool ReadCFOEmulationEnabled(std::optional<uint32_t> val = std::nullopt); // B30
420 : // Bit 29 Reserved
421 : void EnableCFOLoopback(); // B28
422 : void DisableCFOLoopback(); // B28
423 : bool ReadCFOLoopback(std::optional<uint32_t> val = std::nullopt); // B28
424 : void ResetDDRWriteAddress(); // B27
425 : bool ReadResetDDRWriteAddress(std::optional<uint32_t> val = std::nullopt); // B27
426 : void ResetDDRReadAddress(); // B26
427 : bool ReadResetDDRReadAddress(std::optional<uint32_t> val = std::nullopt); // B26
428 : void ResetDDR(); // B25
429 : bool ReadResetDDR(std::optional<uint32_t> val = std::nullopt); // B25
430 : void EnableCFOEmulatorDRP(); // B24
431 : void DisableCFOEmulatorDRP(); // B24
432 : bool ReadCFOEmulatorDRP(std::optional<uint32_t> val = std::nullopt); // B24
433 : void EnableAutogenDRP(); // B23
434 : void DisableAutogenDRP(); // B23
435 : bool ReadAutogenDRP(std::optional<uint32_t> val = std::nullopt); // B23
436 : void EnableSoftwareDRP(); // alias to DisableAutogenDRP()
437 : void DisableSoftwareDRP(); // B23
438 : bool ReadSoftwareDRP(std::optional<uint32_t> val = std::nullopt); // alias to EnableAutogenDRP()
439 : void EnableKillTimeoutROCs(); // B22
440 : void DisableKillTimeoutROCs(); // B22
441 : bool ReadKillTimeoutROCs(std::optional<uint32_t> val = std::nullopt); // B22
442 : virtual void ResetPCIe() override; // B21
443 : bool ReadResetPCIe(std::optional<uint32_t> val = std::nullopt); // B21
444 : // Bit 20 Reserved
445 : void EnableDownLED0(); // B19
446 : void DisableDownLED0(); // B19
447 : bool ReadDownLED0State(std::optional<uint32_t> val = std::nullopt); // B19
448 : void EnableUpLED1(); // B18
449 : void DisableUpLED1(); // B18
450 : bool ReadUpLED1State(std::optional<uint32_t> val = std::nullopt); // B18
451 : void EnableUpLED0(); // B17
452 : void DisableUpLED0(); // B17
453 : bool ReadUpLED0State(std::optional<uint32_t> val = std::nullopt); // B17
454 : void EnableLED6(); // B16
455 : void DisableLED6(); // B16
456 : bool ReadLED6State(std::optional<uint32_t> val = std::nullopt); // B16
457 : void EnableLEDs();
458 : void DisableLEDs();
459 : virtual void FlashLEDs() override;
460 :
461 : void SetCFOEmulationMode(); // B15
462 : void ClearCFOEmulationMode(); // B15
463 : bool ReadCFOEmulationMode(std::optional<uint32_t> val = std::nullopt); // B15
464 : // Bit 14 Reserved
465 : void SetDataFilterEnable(); // B13
466 : void ClearDataFilterEnable(); // B13
467 : bool ReadDataFilterEnable(std::optional<uint32_t> val = std::nullopt); // B13
468 : void SetDRPPrefetchEnable(); // B12
469 : void ClearDRPPrefetchEnable(); // B12
470 : bool ReadDRPPrefetchEnable(std::optional<uint32_t> val = std::nullopt); // B12
471 : void ROCInterfaceSoftReset(); // B11
472 : bool ReadROCInterfaceSoftReset(std::optional<uint32_t> val = std::nullopt); // B11
473 : void EnableDropDataToEmulateEventBuilding(); // B10
474 : void DisableDropDataToEmulateEventBuilding(); // B10
475 : bool ReadDropDataToEmulateEventBuilding(std::optional<uint32_t> val = std::nullopt); // B10
476 : // void SetPunchEnable(); // B9 implemented for CFO and DTC
477 : // void ClearPunchEnable(); // B9 implemented for CFO and DTC
478 : // bool ReadPunchEnable(std::optional<uint32_t> val = std::nullopt); // B9 implemented for CFO and DTC
479 : // void ResetSERDES(); // B8 implemented for CFO and DTC
480 : // bool ReadResetSERDES(std::optional<uint32_t> val = std::nullopt); // B8 implemented for CFO and DTC
481 : void SetExternalCFOSampleEdgeMode(int forceCFOedge); // B6:5
482 : int ReadExternalCFOSampleEdgeMode(std::optional<uint32_t> val); // B6:5
483 : int ToggleExternalCFOSampleEdge(); // B5 only
484 : void SetRTFPunchedClockEdge(bool posedge); // B7
485 : bool ReadRTFPunchedClockEdge(std::optional<uint32_t> val = std::nullopt); // B7
486 : int ToggleRTFPunchedClockEdge(); // B7
487 : void SetExternalFanoutClockInput(); // B4
488 : void SetInternalFanoutClockInput(); // B4
489 : bool ReadFanoutClockInput(std::optional<uint32_t> val = std::nullopt); // B4
490 : // void RunCFOEmulatorLoopbackTest(); // B3 implemented for CFO and DTC
491 : void EnableDCSReception(); // B2
492 : void DisableDCSReception(); // B2
493 : bool ReadDCSReception(std::optional<uint32_t> val = std::nullopt); // B2
494 : // Bit 1 Reserved
495 : // Bit 0 Reserved
496 : RegisterFormatter FormatDTCControl();
497 :
498 : void SetCFOSamplePermanentOffset(int permanentOffset);
499 : int ReadCFOSamplePermanentOffset(std::optional<uint32_t> val = std::nullopt);
500 :
501 : // DMA Transfer Length Register
502 : void SetTriggerDMATransferLength(uint16_t length);
503 : uint16_t ReadTriggerDMATransferLength(std::optional<uint32_t> val = std::nullopt);
504 : void SetMinDMATransferLength(uint16_t length);
505 : uint16_t ReadMinDMATransferLength(std::optional<uint32_t> val = std::nullopt);
506 : RegisterFormatter FormatDMATransferLength();
507 :
508 : // SERDES Loopback Enable Register
509 : void SetSERDESLoopbackMode(DTC_Link_ID const& link, const DTC_SERDESLoopbackMode& mode);
510 : DTC_SERDESLoopbackMode ReadSERDESLoopback(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
511 : RegisterFormatter FormatSERDESLoopbackEnable();
512 :
513 : // Clock Status Register
514 : bool ReadSERDESOscillatorIICError(std::optional<uint32_t> val = std::nullopt);
515 : bool ReadDDROscillatorIICError(std::optional<uint32_t> val = std::nullopt);
516 : RegisterFormatter FormatClockOscillatorStatus();
517 :
518 : // ROC Emulation Enable Register
519 0 : void EnableROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation);
520 0 : void DisableROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation);
521 : bool ReadROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation, std::optional<uint32_t> val = std::nullopt);
522 : void SetROCEmulatorMask(uint32_t rocEnableMask);
523 : uint32_t ReadROCEmulatorMask(std::optional<uint32_t> val = std::nullopt);
524 : RegisterFormatter FormatROCEmulationEnable();
525 :
526 : // Link Enable Register
527 : void EnableReceiveCFOLink();
528 : void DisableReceiveCFOLink();
529 : void EnableTransmitCFOLink();
530 : void DisableTransmitCFOLink();
531 : void EnableLink(DTC_Link_ID const& link, const DTC_LinkEnableMode& mode = DTC_LinkEnableMode());
532 : void DisableLink(DTC_Link_ID const& link, const DTC_LinkEnableMode& mode = DTC_LinkEnableMode());
533 : DTC_LinkEnableMode ReadLinkEnabled(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
534 : uint32_t ReadLinkEnabledData();
535 : bool ReadBlockNullHeartbeatsToROC(std::optional<uint32_t> val = std::nullopt);
536 : void SetBlockNullHeartbeatsToROC(bool enable);
537 : bool ReadResequenceNonNullEvents(std::optional<uint32_t> val = std::nullopt);
538 : void SetResequenceNonNullEvents(bool enable);
539 : bool ReadAutoGenDRPPerLink(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
540 : void SetAutoGenDRPPerLink(DTC_Link_ID const& link, bool enable);
541 : RegisterFormatter FormatLinkEnable();
542 :
543 : // SERDES Reset Register
544 : void ResetSERDESTX(DTC_Link_ID const& link, int interval = 100000);
545 : bool ReadResetSERDESTX(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
546 : void ResetSERDESRX(DTC_Link_ID const& link, int interval = 100000);
547 : bool ReadResetSERDESRX(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
548 : void ResetSERDESPLL(const DTC_PLL_ID& pll, int interval = 100000);
549 : bool ReadResetSERDESPLL(const DTC_PLL_ID& pll, std::optional<uint32_t> val = std::nullopt);
550 : void ResetSERDES(DTC_Link_ID const& link, int interval = 100000);
551 : bool ReadResetSERDES(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
552 : RegisterFormatter FormatSERDESReset();
553 :
554 : // Link Diagnostic FIFOs
555 : DTCLib::RegisterFormatter FormatRXDiagFifo(DTC_Link_ID const& link);
556 : DTCLib::RegisterFormatter FormatTXDiagFifo(DTC_Link_ID const& link);
557 :
558 : // SERDES RX Disparity Error Register
559 : DTC_SERDESRXDisparityError ReadSERDESRXDisparityError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
560 : RegisterFormatter FormatSERDESRXDisparityError();
561 :
562 : // SERDES Character Not In Table Error Register
563 : DTC_CharacterNotInTableError ReadSERDESRXCharacterNotInTableError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
564 : RegisterFormatter FormatSERDESRXCharacterNotInTableError();
565 :
566 : // SERDES Unlock Error Register
567 : bool ReadSERDESCDRUnlockError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
568 : bool ReadSERDESPLLUnlockError(const DTC_PLL_ID& pll, std::optional<uint32_t> val = std::nullopt);
569 : RegisterFormatter FormatSERDESUnlockError();
570 :
571 : // SERDES PLL Locked Register
572 : bool ReadSERDESPLLLocked(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
573 : RegisterFormatter FormatSERDESPLLLocked();
574 :
575 : // SERDES PLL Power Down
576 : void EnableSERDESPLL(DTC_Link_ID const& link);
577 : void DisableSERDESPLL(DTC_Link_ID const& link);
578 : bool ReadSERDESPLLPowerDown(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
579 : RegisterFormatter FormatSERDESPLLPowerDown();
580 :
581 : // SERDES RX Status Register
582 : DTC_RXStatus ReadSERDESRXStatus(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
583 : RegisterFormatter FormatSERDESRXStatus();
584 :
585 : // SERDES Reset Done Register
586 : bool ReadResetRXFSMSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
587 : bool ReadResetRXSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
588 : bool ReadResetTXFSMSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
589 : bool ReadResetTXSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
590 : RegisterFormatter FormatSERDESResetDone();
591 :
592 : // SERDES CDR Lock Register
593 : bool ReadSERDESRXCDRLock(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
594 : RegisterFormatter FormatRXCDRLockStatus();
595 :
596 : // DMA Timeout Preset Regsiter
597 : void SetDMATimeoutPreset(uint32_t preset);
598 : uint32_t ReadDMATimeoutPreset(std::optional<uint32_t> val = std::nullopt);
599 : RegisterFormatter FormatDMATimeoutPreset();
600 :
601 : // ROC Timeout (Header Packet to All Packets Received) Preset Register
602 : void SetROCTimeoutPreset(uint32_t preset);
603 : uint32_t ReadROCTimeoutPreset(std::optional<uint32_t> val = std::nullopt);
604 : RegisterFormatter FormatROCReplyTimeout();
605 :
606 : // ROC Timeout Error Register — DEPRECATED: 0x914C no longer implemented in hardware
607 : void ClearROCTimeoutError(DTC_Link_ID const& link);
608 : bool ReadROCTimeoutError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
609 : uint32_t ReadROCReplyTimeoutErrorRegister(); // DEPRECATED
610 : RegisterFormatter FormatROCReplyTimeoutError();
611 :
612 : //----------------- Hardware Event Building configuration -----------------------
613 :
614 : // EVB Network Partition ID / EVB Network Local MAC Index Register
615 : void SetEVBInfo(uint8_t dtcid, uint8_t mode, uint8_t partitionId, uint8_t macByte);
616 : void SetDTCID(uint8_t dtcid);
617 : uint8_t ReadDTCID(std::optional<uint32_t> val = std::nullopt);
618 : void SetEVBMode(uint8_t mode);
619 : uint8_t ReadEVBMode(std::optional<uint32_t> val = std::nullopt);
620 : void SetEVBLocalParitionID(uint8_t id);
621 : uint8_t ReadEVBLocalParitionID(std::optional<uint32_t> val = std::nullopt);
622 : void SetEVBLocalMACAddress(uint8_t macByte);
623 : uint8_t ReadEVBLocalMACAddress(std::optional<uint32_t> val = std::nullopt);
624 : RegisterFormatter FormatEVBLocalParitionIDMACIndex();
625 :
626 : // EVB Cluster Config
627 : void SetEVBClusterInfo(uint16_t deadTime, uint8_t baseDTCAddress, uint8_t numOfDTCs);
628 : void SetEVBDeadTime(uint16_t deadTime);
629 : uint16_t ReadEVBDeadTime(std::optional<uint32_t> val = std::nullopt);
630 : void SetEVBStartNode(uint8_t node);
631 : uint8_t ReadEVBStartNode(std::optional<uint32_t> val = std::nullopt);
632 : void SetEVBNumberOfDestinationNodes(uint8_t number);
633 : uint8_t ReadEVBNumberOfDestinationNodes(std::optional<uint32_t> val = std::nullopt);
634 : RegisterFormatter FormatEVBClusterInfo();
635 :
636 : // EVB Packet Control
637 : void SetEVBPacketControlInfo(uint16_t idlePacketWordCount, uint8_t interpacketGap, uint8_t loopbackCalibratedOffset);
638 : uint16_t ReadEVBIdlePacketWordCount(std::optional<uint32_t> val = std::nullopt);
639 : uint8_t ReadEVBInterpacketGap(std::optional<uint32_t> val = std::nullopt);
640 : uint8_t ReadEVBLoopbackCalibratedOffset(std::optional<uint32_t> val = std::nullopt);
641 : RegisterFormatter FormatEVBPacketControlInfo();
642 :
643 : // EVB Idle Burst (0x9170)
644 : void SetEVBIdleBurst(uint16_t count);
645 : uint16_t ReadEVBIdleBurst(std::optional<uint32_t> val = std::nullopt);
646 : RegisterFormatter FormatEVBIdleBurst();
647 :
648 : // EVB Resend Count (0x9174, read-only, SoftReset clear, 16-bit wrap)
649 : uint16_t ReadEVBResendsServed(std::optional<uint32_t> val = std::nullopt);
650 : uint16_t ReadEVBResendsRequested(std::optional<uint32_t> val = std::nullopt);
651 : RegisterFormatter FormatEVBResendCount();
652 :
653 : // EVB Stats
654 : uint32_t ReadEVBStats(DTC_EVBStatsType type, uint8_t dtc_mac, std::optional<uint32_t> val = std::nullopt);
655 : RegisterFormatter FormatEVBStats(DTC_EVBStatsType type = DTC_EVBStatsType::DTC_EVBStatsType_All);
656 : std::chrono::time_point<std::chrono::steady_clock> EVB_startDataTime, EVB_endDataTime;
657 :
658 : //----------------- end Hardware Event Building configuration -----------------------
659 :
660 : // SERDES Oscillator Registers
661 : bool ReadSERDESOscillatorIICInterfaceReset(std::optional<uint32_t> val = std::nullopt);
662 : void ResetSERDESOscillatorIICInterface();
663 :
664 : DTC_SerdesClockSpeed ReadSERDESOscillatorClock(std::optional<uint32_t> val = std::nullopt);
665 : void SetSERDESOscillatorClock(DTC_SerdesClockSpeed speed);
666 : void SetTimingOscillatorClock(uint32_t freq);
667 : RegisterFormatter FormatSERDESOscillatorControl();
668 :
669 : // FIFO Full Error Flags Registers
670 : void ClearFIFOFullErrorFlags(DTC_Link_ID const& link);
671 : DTC_FIFOFullErrorFlags ReadFIFOFullErrorFlags(DTC_Link_ID const& link, std::optional<uint32_t> val0 = std::nullopt, std::optional<uint32_t> val1 = std::nullopt, std::optional<uint32_t> val2 = std::nullopt);
672 : RegisterFormatter FormatFIFOFullErrorFlag0();
673 : RegisterFormatter FormatFIFOFullErrorFlag1();
674 : RegisterFormatter FormatFIFOFullErrorFlag2();
675 :
676 : // Receive Packet Error Register
677 : void ClearPacketError(DTC_Link_ID const& link);
678 : bool ReadPacketError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
679 : void ClearPacketCRCError(DTC_Link_ID const& link);
680 : bool ReadPacketCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
681 : RegisterFormatter FormatReceivePacketError();
682 :
683 : // CFO Emulation Timestamp Registers
684 : void SetCFOEmulationTimestamp(const DTC_EventWindowTag& ts);
685 : DTC_EventWindowTag ReadCFOEmulationTimestamp(std::optional<uint32_t> val = std::nullopt);
686 : RegisterFormatter FormatCFOEmulationTimestampLow();
687 : RegisterFormatter FormatCFOEmulationTimestampHigh();
688 :
689 : // CFO Emulation Heartbeat Interval Regsister
690 : void SetCFOEmulationEventWindowInterval(uint32_t interval);
691 : uint32_t ReadCFOEmulationEventWindowInterval(std::optional<uint32_t> val = std::nullopt);
692 : RegisterFormatter FormatCFOEmulationEventWindowInterval();
693 :
694 : // CFO Emulation Number of Heartbeats Register
695 : void SetCFOEmulationNumHeartbeats(uint32_t numHeartbeats);
696 : uint32_t ReadCFOEmulationNumHeartbeats(std::optional<uint32_t> val = std::nullopt);
697 : RegisterFormatter FormatCFOEmulationNumHeartbeats();
698 :
699 : // CFO Emulation Number of Packets Registers
700 : void SetROCEmulationNumPackets(DTC_Link_ID const& link, uint16_t numPackets);
701 : uint16_t ReadROCEmulationNumPackets(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
702 : RegisterFormatter FormatROCEmulationNumPacketsLink01();
703 : RegisterFormatter FormatROCEmulationNumPacketsLink23();
704 : RegisterFormatter FormatROCEmulationNumPacketsLink45();
705 :
706 : // CFO Emulation Loopback Delay Measure
707 : uint32_t ReadCFOEmulationLoopbackDelayMeasure(std::optional<uint32_t> val = std::nullopt);
708 : RegisterFormatter FormatCFOEmulationLoopbackDelayMeasure();
709 :
710 : // CFO Emulation Number of Null Heartbeats Register
711 : void SetCFOEmulationNumNullHeartbeats(const uint32_t& count);
712 : uint32_t ReadCFOEmulationNumNullHeartbeats(std::optional<uint32_t> val = std::nullopt);
713 : RegisterFormatter FormatCFOEmulationNumNullHeartbeats();
714 :
715 : // CFO Event Mode Required Mask (required bits in event mode for CFO emulation to send a heartbeat. 1 uses them)
716 : // The bits that are required. If a mask-bit is 0, it's accepted anyway.
717 : // If a mask-bit is 1, then the eventMode-bit also needs to be 1 to be accepted.
718 : void SetCFOEventModeRequiredMask(const uint32_t& mask);
719 : uint32_t ReadCFOEventModeRequiredMask(std::optional<uint32_t> val = std::nullopt);
720 : RegisterFormatter FormatCFOEventModeRequiredMask();
721 :
722 : // CFO Emulation Event Mode Bytes Registers
723 : void SetCFOEmulationEventMode(const uint64_t& eventMode);
724 : uint64_t ReadCFOEmulationEventMode();
725 : void SetCFOEmulationModeByte(const uint8_t& byteNum, uint8_t data);
726 : uint8_t ReadCFOEmulationModeByte(const uint8_t& byteNum, std::optional<uint32_t> val = std::nullopt);
727 : RegisterFormatter FormatCFOEmulationModeBytes03();
728 : RegisterFormatter FormatCFOEmulationModeBytes45();
729 :
730 : // CFO Emulation Debug Packet Type Register
731 : // void EnableDebugPacketMode();
732 : // void DisableDebugPacketMode();
733 : // bool ReadDebugPacketMode(std::optional<uint32_t> val = std::nullopt);
734 : // void SetCFOEmulationDebugType(DTC_DebugType type);
735 : // DTC_DebugType ReadCFOEmulationDebugType(std::optional<uint32_t> val = std::nullopt);
736 : // RegisterFormatter FormatCFOEmulationDebugPacketType();
737 :
738 : // RX Packet Count Error Flags Register
739 : bool ReadRXPacketCountErrorFlags(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
740 : void ClearRXPacketCountErrorFlags(DTC_Link_ID const& link);
741 : void ClearRXPacketCountErrorFlags();
742 : RegisterFormatter FormatRXPacketCountErrorFlags();
743 :
744 : // Detector Emulation DMA Count Register
745 : void SetDetectorEmulationDMACount(uint32_t count);
746 : uint32_t ReadDetectorEmulationDMACount(std::optional<uint32_t> val = std::nullopt);
747 : RegisterFormatter FormatDetectorEmulationDMACount();
748 :
749 : // Detector Emulation DMA Delay Count Register
750 : void SetDetectorEmulationDMADelayCount(uint32_t count);
751 : uint32_t ReadDetectorEmulationDMADelayCount(std::optional<uint32_t> val = std::nullopt);
752 : RegisterFormatter FormatDetectorEmulationDMADelayCount();
753 :
754 : // Detector Emulation Control Registers
755 : void EnableDetectorEmulatorMode();
756 : void DisableDetectorEmulatorMode();
757 : bool ReadDetectorEmulatorMode(std::optional<uint32_t> val = std::nullopt);
758 : void EnableDetectorEmulator();
759 : void DisableDetectorEmulator();
760 : bool ReadDetectorEmulatorEnable(std::optional<uint32_t> val = std::nullopt);
761 : bool ReadDetectorEmulatorEnableClear(std::optional<uint32_t> val = std::nullopt);
762 : /// <summary>
763 : /// Return the current value of the "Detector Emulator In Use" virtual register
764 : /// </summary>
765 : /// <returns>Whether the DTC Detector Emulator has been set up</returns>
766 0 : bool IsDetectorEmulatorInUse() const { return usingDetectorEmulator_; }
767 : /// <summary>
768 : /// Set the "Detector Emulator In Use" virtual register to true
769 : /// </summary>
770 0 : void SetDetectorEmulatorInUse()
771 : {
772 : #ifndef __CLING__
773 0 : TLOG(TLVL_WARNING) << "DTC_Registers::SetDetectorEmulatorInUse: Enabling Detector Emulator!";
774 : #endif
775 0 : usingDetectorEmulator_ = true;
776 0 : }
777 : void ClearDetectorEmulatorInUse();
778 : RegisterFormatter FormatDetectorEmulationControl0();
779 : RegisterFormatter FormatDetectorEmulationControl1();
780 :
781 : // DDR Event Data Local Start Address Register
782 : void SetDDRDataLocalStartAddress(uint32_t address);
783 : uint32_t ReadDDRDataLocalStartAddress(std::optional<uint32_t> val = std::nullopt);
784 : RegisterFormatter FormatDDRDataLocalStartAddress();
785 :
786 : // DDR Event Data Local End Address Register
787 : void SetDDRDataLocalEndAddress(uint32_t address);
788 : uint32_t ReadDDRDataLocalEndAddress(std::optional<uint32_t> val = std::nullopt);
789 : RegisterFormatter FormatDDRDataLocalEndAddress();
790 :
791 : // CFO Emulator Data Request Interpacket Delay
792 : uint32_t ReadCFOEmulatorInterpacketDelay(std::optional<uint32_t> val = std::nullopt);
793 : RegisterFormatter FormatCFOEmulatorInterpacketDelay();
794 :
795 : // Ethernet Frame Payload Max Size
796 : uint32_t ReadEthernetPayloadSize(std::optional<uint32_t> val = std::nullopt);
797 : void SetEthernetPayloadSize(uint32_t size);
798 : RegisterFormatter FormatEthernetPayloadSize();
799 :
800 : // CFO Emulation 40 MHz Clock Marker Interval
801 : uint32_t ReadCFOEmulation40MHzMarkerInterval(std::optional<uint32_t> val = std::nullopt);
802 : void SetCFOEmulation40MHzMarkerInterval(uint32_t interval);
803 : RegisterFormatter FormatCFOEmulation40MHzMarkerInterval();
804 :
805 : // CFO Emulation Marker Enables
806 : // bool ReadCFOEmulationEventStartMarkerEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
807 : // void SetCFOEmulationEventStartMarkerEnable(DTC_Link_ID const& link, bool enable);
808 : bool ReadCFO40MHzClockMarkerEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
809 : void SetCFO40MHzClockMarkerEnable(DTC_Link_ID const& link, bool enable);
810 : RegisterFormatter FormatCFO40MHzClockMarkerEnables();
811 :
812 : // ROC Finish Threshold Register
813 : uint8_t ReadROCCommaLimit(std::optional<uint32_t> val = std::nullopt);
814 : void SetROCCommaLimit(uint8_t limit);
815 : RegisterFormatter FormatROCFinishThreshold();
816 :
817 : // SERDES TX PRBS Control
818 : bool ReadTXPRBSForceError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
819 : void SetTXPRBSForceError(DTC_Link_ID const& link);
820 : void ClearTXPRBSForceError(DTC_Link_ID const& link);
821 : DTC_PRBSMode ReadTXPRBSMode(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
822 : void SetTXPRBSMode(DTC_Link_ID const& link, DTC_PRBSMode mode);
823 : RegisterFormatter FormatSERDESTXPRBSControl();
824 :
825 : // SERDES RX PRBS Control
826 : bool ReadRXPRBSError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
827 : DTC_PRBSMode ReadRXPRBSMode(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
828 : void SetRXPRBSMode(DTC_Link_ID const& link, DTC_PRBSMode mode);
829 : RegisterFormatter FormatSERDESRXPRBSControl();
830 :
831 : // DTC Mode Lookup
832 : bool ReadEventModeTableEnable(std::optional<uint32_t> val = std::nullopt);
833 : void SetEventModeTableEnable();
834 : void ClearEventModeTableEnable();
835 : uint8_t ReadEventModeLookupByteSelect(std::optional<uint32_t> val = std::nullopt);
836 : void SetEventModeLookupByteSelect(uint8_t byte);
837 : RegisterFormatter FormatEventModeLookupTableControl();
838 :
839 : // DDR Memory Test Register
840 : bool ReadDDRMemoryTestComplete(std::optional<uint32_t> val = std::nullopt);
841 : bool ReadDDRMemoryTestError(std::optional<uint32_t> val = std::nullopt);
842 : void ClearDDRMemoryTestError();
843 : RegisterFormatter FormatDDRMemoryTestRegister();
844 :
845 : // SERDES Serial Inversion Enable Register
846 : bool ReadInvertSERDESRXInput(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
847 : void SetInvertSERDESRXInput(DTC_Link_ID const& link, bool invert);
848 : bool ReadInvertSERDESTXOutput(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
849 : void SetInvertSERDESTXOutput(DTC_Link_ID const& link, bool invert);
850 : RegisterFormatter FormatSERDESSerialInversionEnable();
851 :
852 : // Jitter Attenuator CSR Register
853 : virtual std::bitset<2> ReadJitterAttenuatorSelect(std::optional<uint32_t> val = std::nullopt) override;
854 : virtual void SetJitterAttenuatorSelect(std::bitset<2> data, bool alsoResetJA = false) override;
855 : virtual bool ReadJitterAttenuatorReset(std::optional<uint32_t> val = std::nullopt) override;
856 : virtual bool ReadJitterAttenuatorLocked(std::optional<uint32_t> val = std::nullopt) override;
857 : virtual void ResetJitterAttenuator() override;
858 : virtual RegisterFormatter FormatJitterAttenuatorCSR() override;
859 :
860 : // void ConfigureJitterAttenuator();
861 :
862 : // SFP IIC Registers
863 : bool ReadSFPIICInterfaceReset(std::optional<uint32_t> val = std::nullopt);
864 : void ResetSFPIICInterface();
865 : void WriteSFPIICInterface(uint8_t device, uint8_t address, uint8_t data);
866 : uint8_t ReadSFPIICInterface(uint8_t device, uint8_t address);
867 : RegisterFormatter FormatSFPIICControl();
868 : RegisterFormatter FormatSFPIICParameterLow();
869 : RegisterFormatter FormatSFPIICParameterHigh();
870 :
871 : // Retransmit Request Count Registers
872 : uint32_t ReadRetransmitRequestCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
873 : void ClearRetransmitRequestCount(DTC_Link_ID const& link);
874 : RegisterFormatter FormatRetransmitRequestCountLink0();
875 : RegisterFormatter FormatRetransmitRequestCountLink1();
876 : RegisterFormatter FormatRetransmitRequestCountLink2();
877 : RegisterFormatter FormatRetransmitRequestCountLink3();
878 : RegisterFormatter FormatRetransmitRequestCountLink4();
879 : RegisterFormatter FormatRetransmitRequestCountLink5();
880 :
881 : // Missed CFO Packet Count Registers
882 : uint32_t ReadMissedCFOPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
883 : void ClearMissedCFOPacketCount(DTC_Link_ID const& link);
884 : RegisterFormatter FormatMissedCFOPacketCountLink0();
885 : RegisterFormatter FormatMissedCFOPacketCountLink1();
886 : RegisterFormatter FormatMissedCFOPacketCountLink2();
887 : RegisterFormatter FormatMissedCFOPacketCountLink3();
888 : RegisterFormatter FormatMissedCFOPacketCountLink4();
889 : RegisterFormatter FormatMissedCFOPacketCountLink5();
890 :
891 : // Local Fragment Drop Count Register
892 : uint32_t ReadLocalFragmentDropCount(std::optional<uint32_t> val = std::nullopt);
893 : void ClearLocalFragmentDropCount();
894 : RegisterFormatter FormatLocalFragmentDropCount();
895 :
896 : // EVB SubEvent Receive Timer Preset
897 : uint32_t ReadEVBSubEventReceiveTimer(std::optional<uint32_t> val = std::nullopt);
898 : void SetEVBSubEventReceiveTimer(uint32_t timer);
899 : RegisterFormatter FormatEVBSubEventReceiveTimer();
900 :
901 : // EVB SERDES PRBS Control / Status Register
902 : bool ReadEVBSERDESPRBSErrorFlag(std::optional<uint32_t> val = std::nullopt);
903 : uint8_t ReadEVBSERDESTXPRBSSEL(std::optional<uint32_t> val = std::nullopt);
904 : void SetEVBSERDESTXPRBSSEL(uint8_t byte);
905 : uint8_t ReadEVBSERDESRXPRBSSEL(std::optional<uint32_t> val = std::nullopt);
906 : void SetEVBSERDESRXPRBSSEL(uint8_t byte);
907 : bool ReadEVBSERDESPRBSForceError(std::optional<uint32_t> val = std::nullopt);
908 : void SetEVBSERDESPRBSForceError(bool flag);
909 : void ToggleEVBSERDESPRBSForceError();
910 : bool ReadEVBSERDESPRBSReset(std::optional<uint32_t> val = std::nullopt);
911 : void SetEVBSERDESPRBSReset(bool flag);
912 : void ToggleEVBSERDESPRBSReset();
913 : RegisterFormatter FormatEVBSERDESPRBSControl();
914 :
915 : // Event Builder Error Register
916 : bool ReadEventBuilder_SubEventReceiverFlagsBufferError(std::optional<uint32_t> val = std::nullopt);
917 : bool ReadEventBuilder_EthernetInputFIFOFull(std::optional<uint32_t> val = std::nullopt);
918 : bool ReadEventBuilder_LinkError(std::optional<uint32_t> val = std::nullopt);
919 : bool ReadEventBuilder_TXPacketError(std::optional<uint32_t> val = std::nullopt);
920 : bool ReadEventBuilder_LocalDataPointerFIFOQueueError(std::optional<uint32_t> val = std::nullopt);
921 : bool ReadEventBuilder_TransmitDMAByteCountFIFOFull(std::optional<uint32_t> val = std::nullopt);
922 : RegisterFormatter FormatEventBuilderErrorRegister();
923 :
924 : // SERDES VFIFO Error Register
925 : bool ReadSERDESVFIFO_EgressFIFOFull(std::optional<uint32_t> val = std::nullopt);
926 : bool ReadSERDESVFIFO_IngressFIFOFull(std::optional<uint32_t> val = std::nullopt);
927 : bool ReadSERDESVFIFO_EventByteCountTotalError(std::optional<uint32_t> val = std::nullopt);
928 : bool ReadSERDESVFIFO_LastWordWrittenTimeoutError(std::optional<uint32_t> val = std::nullopt);
929 : bool ReadSERDESVFIFO_FragmentCountError(std::optional<uint32_t> val = std::nullopt);
930 : bool ReadSERDESVFIFO_DDRFullError(std::optional<uint32_t> val = std::nullopt);
931 : RegisterFormatter FormatSERDESVFIFOError();
932 :
933 : // PCI VFIFO Error Register
934 : bool ReadPCIVFIFO_DDRFull(std::optional<uint32_t> val = std::nullopt);
935 : bool ReadPCIVFIFO_MemoryMappedWriteCompleteFIFOFull(std::optional<uint32_t> val = std::nullopt);
936 : bool ReadPCIVFIFO_PCIWriteEventFIFOFull(std::optional<uint32_t> val = std::nullopt);
937 : bool ReadPCIVFIFO_LocalDataPointerFIFOFull(std::optional<uint32_t> val = std::nullopt);
938 : bool ReadPCIVFIFO_EgressFIFOFull(std::optional<uint32_t> val = std::nullopt);
939 : bool ReadPCIVFIFO_RXBufferSelectFIFOFull(std::optional<uint32_t> val = std::nullopt);
940 : bool ReadPCIVFIFO_IngressFIFOFull(std::optional<uint32_t> val = std::nullopt);
941 : bool ReadPCIVFIFO_EventByteCountTotalError(std::optional<uint32_t> val = std::nullopt);
942 : RegisterFormatter FormatPCIVFIFOError();
943 :
944 : // ROC Link Error Registers
945 : bool ReadROCLink_ROCDataRequestSyncError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
946 : bool ReadROCLink_RXPacketCountError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
947 : bool ReadROCLink_RXPacketError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
948 : bool ReadROCLink_RXPacketCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
949 : bool ReadROCLink_DataPendingTimeoutError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
950 : bool ReadROCLink_ReceiveDataPacketCountError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
951 : RegisterFormatter FormatRocLink0Error();
952 : RegisterFormatter FormatRocLink1Error();
953 : RegisterFormatter FormatRocLink2Error();
954 : RegisterFormatter FormatRocLink3Error();
955 : RegisterFormatter FormatRocLink4Error();
956 : RegisterFormatter FormatRocLink5Error();
957 :
958 : // CFO Link Error Register
959 : uint32_t ReadCFOLinkErrorRegister();
960 : int ReadCFOMeasuredMarkerPosition(std::optional<uint32_t> val = std::nullopt); // B18:16
961 : int ReadCFOImpliedMarkerOffset(std::optional<uint32_t> val = std::nullopt); // 2 - measured
962 : bool ReadCFOEventStartMarkerTxError(std::optional<uint32_t> val = std::nullopt); // B9
963 : bool ReadCFOClockMarkerTxError(std::optional<uint32_t> val = std::nullopt); // B10
964 : bool ReadCFORTF40MHzPhaseShiftError(std::optional<uint32_t> val = std::nullopt); // B11
965 : bool ReadCFOIllegalMarkerTimingError(std::optional<uint32_t> val = std::nullopt); // B12
966 : bool ReadCFORxToTxDataCorruptionError(std::optional<uint32_t> val = std::nullopt); // B13
967 : RegisterFormatter FormatCFOLinkError();
968 :
969 : // Link Mux Error Register
970 : bool ReadDCSMuxDecodeError(std::optional<uint32_t> val = std::nullopt);
971 : bool ReadDataMuxDecodeError(std::optional<uint32_t> val = std::nullopt);
972 : RegisterFormatter FormatLinkMuxError();
973 :
974 : // SFP Control Status Register
975 : bool ReadSFPPresent(std::optional<uint32_t> val = std::nullopt);
976 : bool ReadSFPLOS(std::optional<uint32_t> val = std::nullopt);
977 : bool ReadSFPTXFault(std::optional<uint32_t> val = std::nullopt);
978 : void EnableSFPRateSelect();
979 : void DisableSFPRateSelect();
980 : bool ReadSFPRateSelect(std::optional<uint32_t> val = std::nullopt);
981 : void DisableSFPTX();
982 : void EnableSFPTX();
983 : bool ReadSFPTXDisable(std::optional<uint32_t> val = std::nullopt);
984 : RegisterFormatter FormatSFPControlStatus();
985 :
986 : // RX CDR Unlock Count Registers
987 : uint32_t ReadRXCDRUnlockCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
988 : void ClearRXCDRUnlockCount(DTC_Link_ID const& link);
989 : RegisterFormatter FormatRXCDRUnlockCountLink0();
990 : RegisterFormatter FormatRXCDRUnlockCountLink1();
991 : RegisterFormatter FormatRXCDRUnlockCountLink2();
992 : RegisterFormatter FormatRXCDRUnlockCountLink3();
993 : RegisterFormatter FormatRXCDRUnlockCountLink4();
994 : RegisterFormatter FormatRXCDRUnlockCountLink5();
995 : RegisterFormatter FormatRXCDRUnlockCountCFOLink();
996 :
997 : // RX Jitter Attenuator Unlock Count Register
998 : uint32_t ReadJitterAttenuatorUnlockCount(std::optional<uint32_t> val = std::nullopt);
999 : void ClearJitterAttenuatorUnlockCount();
1000 : RegisterFormatter FormatJitterAttenuatorUnlockCount();
1001 :
1002 : // RX CFO Link Event Start Character Error Count Register
1003 : uint32_t ReadRXCFOLinkEventStartCharacterErrorCount(std::optional<uint32_t> val = std::nullopt);
1004 : void ClearRXCFOLinkEventStartCharacterErrorCount();
1005 : RegisterFormatter FormatRXCFOLinkEventStartCharacterErrorCount();
1006 :
1007 : // RX CFO Link 40MHz Clock Character Error Count Register
1008 : uint32_t ReadRXCFOLink40MHzCharacterErrorCount(std::optional<uint32_t> val = std::nullopt);
1009 : void ClearRXCFOLink40MHzCharacterErrorCount();
1010 : RegisterFormatter FormatRXCFOLink40MHzCharacterErrorCount();
1011 :
1012 : // Input Buffer Fragment Dump Count
1013 : uint32_t ReadInputBufferFragmentDumpCount(std::optional<uint32_t> val = std::nullopt);
1014 : void ClearInputBufferFragmentDumpCount();
1015 : RegisterFormatter FormatInputBufferFragmentDumpCount();
1016 :
1017 : // Output Buffer Fragment Dump Count
1018 : uint32_t ReadOutputBufferFragmentDumpCount(std::optional<uint32_t> val = std::nullopt);
1019 : void ClearOutputBufferFragmentDumpCount();
1020 : RegisterFormatter FormatOutputBufferFragmentDumpCount();
1021 :
1022 : // RTF Histogram and IDELAY Status Register (Read-Only)
1023 : uint32_t ReadRTFHistIdelay(std::optional<uint32_t> val = std::nullopt);
1024 : RegisterFormatter FormatRTFHistIdelay();
1025 :
1026 : // Software DataRequests
1027 : void SetSoftwareDataRequest(const DTC_EventWindowTag& ts);
1028 : DTC_EventWindowTag ReadSoftwareDataRequest(std::optional<uint32_t> val = std::nullopt);
1029 : RegisterFormatter FormatSoftwareDataRequestLow();
1030 : RegisterFormatter FormatSoftwareDataRequestHigh();
1031 :
1032 : // FPGA PROM Program Data Register
1033 :
1034 : // FPGA PROM Program Status Register
1035 : bool ReadFPGAPROMProgramFIFOFull(std::optional<uint32_t> val = std::nullopt);
1036 : bool ReadFPGAPROMReady(std::optional<uint32_t> val = std::nullopt);
1037 : RegisterFormatter FormatFPGAPROMProgramStatus();
1038 :
1039 : // FPGA Core Access Register
1040 : void ReloadFPGAFirmware();
1041 : bool ReadFPGACoreAccessFIFOFull(std::optional<uint32_t> val = std::nullopt);
1042 : bool ReadFPGACoreAccessFIFOEmpty(std::optional<uint32_t> val = std::nullopt);
1043 : RegisterFormatter FormatFPGACoreAccess();
1044 :
1045 : // Slow Optical Links Control/Status Register
1046 : bool ReadRXOKErrorSlowOpticalLink3(std::optional<uint32_t> val = std::nullopt);
1047 : bool ReadRXOKErrorSlowOpticalLink2(std::optional<uint32_t> val = std::nullopt);
1048 : bool ReadRXOKErrorSlowOpticalLink1(std::optional<uint32_t> val = std::nullopt);
1049 : bool ReadRXOKErrorSlowOpticalLink0(std::optional<uint32_t> val = std::nullopt);
1050 : bool ReadLatchedSpareSMAInputOKError(std::optional<uint32_t> val = std::nullopt);
1051 : void ClearLatchedSpareSMAInputOKError();
1052 : bool ReadLatchedEventMarkerSMAInputOKError(std::optional<uint32_t> val = std::nullopt);
1053 : void ClearLatchedEventMarkerSMASMAInputOKError();
1054 : bool ReadLatchedRXOKErrorSlowOpticalLink3(std::optional<uint32_t> val = std::nullopt);
1055 : void ClearLatchedRXOKErrorSlowOpticalLink3();
1056 : bool ReadLatchedRXOKErrorSlowOpticalLink2(std::optional<uint32_t> val = std::nullopt);
1057 : void ClearLatchedRXOKErrorSlowOpticalLink2();
1058 : bool ReadLatchedRXOKErrorSlowOpticalLink1(std::optional<uint32_t> val = std::nullopt);
1059 : void ClearLatchedRXOKErrorSlowOpticalLink1();
1060 : bool ReadLatchedRXOKErrorSlowOpticalLink0(std::optional<uint32_t> val = std::nullopt);
1061 : void ClearLatchedRXOKErrorSlowOpticalLink0();
1062 : RegisterFormatter FormatSlowOpticalLinkControlStatus();
1063 :
1064 : // Diagnostic SERDES Induce Error Enable Register
1065 : bool ReadSERDESInduceErrorEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1066 : void EnableSERDESInduceError(DTC_Link_ID const& link);
1067 : void DisableSERDESInduceError(DTC_Link_ID const& link);
1068 : RegisterFormatter FormatSERDESInduceErrorEnable();
1069 :
1070 : // Diagnostic SERDES Incude Error Link Registers
1071 : uint32_t ReadSERDESInduceErrorSequenceNumber(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1072 : void SetSERDESInduceErrorSequenceNumber(DTC_Link_ID const& link, uint32_t sequence);
1073 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink0();
1074 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink1();
1075 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink2();
1076 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink3();
1077 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink4();
1078 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink5();
1079 :
1080 : // // DDR Memory Flags Registers
1081 : // DTC_DDRFlags ReadDDRFlags(uint8_t buffer_id);
1082 : // std::bitset<128> ReadDDRLinkBufferFullFlags();
1083 : // std::bitset<128> ReadDDRLinkBufferEmptyFlags();
1084 : // std::bitset<128> ReadDDRLinkBufferHalfFullFlags();
1085 : // std::bitset<128> ReadDDREventBuilderBufferFullFlags();
1086 : // std::bitset<128> ReadDDREventBuilderBufferEmptyFlags();
1087 : // std::bitset<128> ReadDDREventBuilderBufferHalfFullFlags();
1088 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags0();
1089 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags1();
1090 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags2();
1091 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags3();
1092 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags0();
1093 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags1();
1094 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags2();
1095 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags3();
1096 : // RegisterFormatter FormatDDRLinkBufferFullFlags0();
1097 : // RegisterFormatter FormatDDRLinkBufferFullFlags1();
1098 : // RegisterFormatter FormatDDRLinkBufferFullFlags2();
1099 : // RegisterFormatter FormatDDRLinkBufferFullFlags3();
1100 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags0();
1101 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags1();
1102 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags2();
1103 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags3();
1104 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags0();
1105 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags1();
1106 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags2();
1107 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags3();
1108 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags0();
1109 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags1();
1110 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags2();
1111 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags3();
1112 :
1113 : // Data Pending Diagnostic Timer Registers
1114 : uint32_t ReadDataPendingDiagnosticTimer(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1115 : void ResetDataPendingDiagnosticTimerFIFO(DTC_Link_ID const& link);
1116 : RegisterFormatter FormatDataPendingDiagnosticTimerLink0();
1117 : RegisterFormatter FormatDataPendingDiagnosticTimerLink1();
1118 : RegisterFormatter FormatDataPendingDiagnosticTimerLink2();
1119 : RegisterFormatter FormatDataPendingDiagnosticTimerLink3();
1120 : RegisterFormatter FormatDataPendingDiagnosticTimerLink4();
1121 : RegisterFormatter FormatDataPendingDiagnosticTimerLink5();
1122 :
1123 : // SERDES CNIT Error Count
1124 : uint32_t ReadSERDESCharacterNotInTableErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1125 : void ClearSERDESCharacterNotInTableErrorCount(DTC_Link_ID const& link);
1126 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink0();
1127 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink1();
1128 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink2();
1129 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink3();
1130 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink4();
1131 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink5();
1132 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountCFOLink();
1133 :
1134 : // SERDES RX Disparity Error Count
1135 : uint32_t ReadSERDESRXDisparityErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1136 : void ClearSERDESRXDisparityErrorCount(DTC_Link_ID const& link);
1137 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink0();
1138 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink1();
1139 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink2();
1140 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink3();
1141 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink4();
1142 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink5();
1143 : RegisterFormatter FormatSERDESRXDisparityErrorCountCFOLink();
1144 :
1145 : // SERDES RX PRBS Error Count
1146 : uint32_t ReadSERDESRXPRBSErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1147 : void ClearSERDESRXPRBSErrorCount(DTC_Link_ID const& link);
1148 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink0();
1149 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink1();
1150 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink2();
1151 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink3();
1152 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink4();
1153 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink5();
1154 : RegisterFormatter FormatSERDESRXPRBSErrorCountCFOLink();
1155 :
1156 : // SERDES RX CRC Error Count
1157 : uint32_t ReadSERDESRXCRCErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1158 : void ClearSERDESRXCRCErrorCount(DTC_Link_ID const& link);
1159 : RegisterFormatter FormatSERDESRXCRCErrorCountLink0();
1160 : RegisterFormatter FormatSERDESRXCRCErrorCountLink1();
1161 : RegisterFormatter FormatSERDESRXCRCErrorCountLink2();
1162 : RegisterFormatter FormatSERDESRXCRCErrorCountLink3();
1163 : RegisterFormatter FormatSERDESRXCRCErrorCountLink4();
1164 : RegisterFormatter FormatSERDESRXCRCErrorCountLink5();
1165 : RegisterFormatter FormatSERDESRXCRCErrorCountCFOLink();
1166 :
1167 : // SERDES RX CRC Error Control
1168 : bool ReadEnableInduceSERDESRXCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1169 : void EnableInduceSERDESRXCRCError(DTC_Link_ID const& link);
1170 : void DisableInduceSERDESRXCRCError(DTC_Link_ID const& link);
1171 : RegisterFormatter FormatSERDESRXCRCErrorControl();
1172 :
1173 : uint32_t ReadEVBSERDESRXPacketErrorCounter(std::optional<uint32_t> val = std::nullopt);
1174 : void ClearEVBSERDESRXPacketErrorCounter();
1175 : RegisterFormatter FormatEVBSERDESRXPacketErrorCounter();
1176 :
1177 : // Jitter Attenuator SERDES RX Recovered Clock LOS Counter
1178 : uint32_t ReadJitterAttenuatorRecoveredClockLOSCount(std::optional<uint32_t> val = std::nullopt);
1179 : void ClearJitterAttenuatorRecoveredClockLOSCount();
1180 : RegisterFormatter FormatJitterAttenuatorRecoveredClockLOSCount();
1181 :
1182 : // Jitter Attenuator SERDES RX External Clock LOS Counter
1183 : uint32_t ReadJitterAttenuatorExternalClockLOSCount(std::optional<uint32_t> val = std::nullopt);
1184 : void ClearJitterAttenuatorExternalClockLOSCount();
1185 : RegisterFormatter FormatJitterAttenuatorExternalClockLOSCount();
1186 :
1187 : // ROC Emulator Interpacket Delay
1188 : uint32_t ReadROCEmulatorInterpacketDelay(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1189 : void SetROCEmulatorInterpacketDelay(DTC_Link_ID const& link, uint32_t delay);
1190 : RegisterFormatter FormatROCEmulatorInterpacketDelayLink0();
1191 :
1192 : // TX Data Request Packet Count
1193 : uint32_t ReadTXDataRequestPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1194 : RegisterFormatter FormatTXDataRequestPacketCountLink(DTC_Link_ID const& link);
1195 : DTC_Register GetTXDataRequestPacketCountLinkRegister(DTC_Link_ID const& link);
1196 :
1197 : RegisterFormatter FormatCFOTXClockMarkerCountLink6();
1198 : uint32_t ReadCFOTXClockMarkerCountLink6(std::optional<uint32_t> val = std::nullopt);
1199 :
1200 : // Receive DH Timeout Count
1201 : uint32_t ReadReceiveDHTimeoutCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1202 : DTC_Register GetReceiveDHTimeoutCountLinkRegister(DTC_Link_ID const& link);
1203 :
1204 : // TX Heartbeat Packet Count
1205 : uint32_t ReadTXHeartbeatPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1206 : RegisterFormatter FormatTXHeartbeatPacketCountLink(DTC_Link_ID const& link);
1207 : DTC_Register GetTXHeartbeatPacketCountLinkRegister(DTC_Link_ID const& link);
1208 :
1209 : // TX Data Request Packet Count
1210 : uint32_t ReadTXEventWindowMarkerCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1211 : RegisterFormatter FormatTXEventWindowMarkerCountLink(DTC_Link_ID const& link);
1212 : DTC_Register GetTXEventWindowMarkerCountLinkRegister(DTC_Link_ID const& link);
1213 :
1214 : // TX Null Heartbeat Packet Count
1215 : uint32_t ReadTXNullHeartbeatCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1216 : RegisterFormatter FormatTXNullHeartbeatCountLink(DTC_Link_ID const& link);
1217 : DTC_Register GetTXNullHeartbeatCountLinkRegister(DTC_Link_ID const& link);
1218 :
1219 : // TX Blocked (Suppressed) Heartbeat Count
1220 : uint32_t ReadTXBlockedHeartbeatCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1221 : RegisterFormatter FormatTXBlockedHeartbeatCountLink(DTC_Link_ID const& link);
1222 : DTC_Register GetTXBlockedHeartbeatCountLinkRegister(DTC_Link_ID const& link);
1223 :
1224 : // TX Non-null Heartbeat Count
1225 : uint32_t ReadTXNonnullHeartbeatCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1226 : RegisterFormatter FormatTXNonnullHeartbeatCountLink(DTC_Link_ID const& link);
1227 : DTC_Register GetTXNonnullHeartbeatCountLinkRegister(DTC_Link_ID const& link);
1228 :
1229 : // RX Data Header Packet Count
1230 : uint32_t ReadRXDataHeaderPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1231 : RegisterFormatter FormatRXDataHeaderPacketCountLink(DTC_Link_ID const& link);
1232 : DTC_Register GetRXDataHeaderPacketCountLinkRegister(DTC_Link_ID const& link);
1233 :
1234 : // CFO CDC Diagnostic (Parity Mismatch & Batch Slip Counts)
1235 : uint32_t ReadCFOCDCDiag(std::optional<uint32_t> val = std::nullopt);
1236 : RegisterFormatter FormatCFOCDCDiag();
1237 :
1238 : // Time Alive Register (override to append EVB firmware version)
1239 : RegisterFormatter FormatDeviceTimeAlive() override;
1240 :
1241 : // EVB Firmware Version and High Level Counters (0x9200/0x9204/0x9208/0x920C)
1242 : std::string ReadEVBFirmwareVersion(std::optional<uint32_t> val = std::nullopt); // 0x9200 [15:0] as "Bx.yy"
1243 : uint32_t ReadEVBHighLevelCounters0(std::optional<uint32_t> val = std::nullopt); // 0x9200 raw
1244 : uint32_t ReadEVBHighLevelCounters1(std::optional<uint32_t> val = std::nullopt); // 0x9204 raw
1245 : uint32_t ReadEVBHighLevelCounters2(std::optional<uint32_t> val = std::nullopt); // 0x9208 raw
1246 : uint32_t ReadEVBHighLevelCounters3(std::optional<uint32_t> val = std::nullopt); // 0x920C raw
1247 : // EVB3 self-chunk cap (0x9178) and stall-time counters (0x9210-0x9228)
1248 : uint16_t ReadEVBLocalChunkCap(std::optional<uint32_t> val = std::nullopt);
1249 : void SetEVBLocalChunkCap(uint16_t words); // [15:0]; upper half kept
1250 : uint32_t ReadEVBRemoteChunkControl(std::optional<uint32_t> val = std::nullopt); // 0x917C raw
1251 : // EVB3 TX packet history (0x925C status, 0x91F0 readback; hw agent 2026-10-13). The log records every
1252 : // 10GbE TX packet until a peer requests a retransmission, then freezes: the entries around the peer's
1253 : // last-acknowledged sequence number show what was on the wire when the drop happened.
1254 : struct EVBTxHistoryEntry
1255 : {
1256 : bool firstOfSubevent{false}; ///< [28]
1257 : bool lastOfSubevent{false}; ///< [27]
1258 : bool hasData{false}; ///< [26] 1 = data, 0 = null
1259 : uint8_t destinationOffset{0}; ///< [25:21] node offset 0..31
1260 : uint8_t sequence{0}; ///< [20:13]
1261 : uint16_t sizeWords{0}; ///< [12:0] packet size in 64-bit words
1262 : uint32_t raw{0};
1263 : };
1264 : struct EVBTxHistory
1265 : {
1266 : uint32_t statusRaw{0};
1267 : bool frozen{false}; ///< [31]
1268 : uint8_t firstResendDestination{0}; ///< [30:26]
1269 : uint8_t peerLastAckSequence{0}; ///< [25:18]
1270 : uint16_t entriesWritten{0}; ///< [9:0]
1271 : std::vector<EVBTxHistoryEntry> entries; ///< entries 0..entriesWritten-1 (only read when frozen or asked)
1272 : bool endMarkerSeen{false}; ///< a read past the end returned 0xFFFFFFFF
1273 : bool alreadyWalked{false}; ///< the very first 0x91F0 read returned 0xFFFFFFFF: the log was walked earlier this run
1274 : bool ringWrapped{false}; ///< entries written == 1023: ring full, entries start at the oldest survivor; the last entry is the one just before the freeze
1275 : };
1276 : static EVBTxHistoryEntry DecodeEVBTxHistoryEntry(uint32_t raw);
1277 : uint32_t ReadEVBTxHistoryStatus(std::optional<uint32_t> val = std::nullopt); // 0x925C raw
1278 : uint16_t ReadEVBRxIllegalDestCount(std::optional<uint32_t> val = std::nullopt); // 0x9180 [15:0]: frames the switch forwarded here that were for another DTC
1279 : /// Read 0x925C and, when readEntries is set, drain 0x91F0 (count+1 reads: the first loads the output).
1280 : /// The read pointer only rewinds on SoftReset, so the log can be walked ONCE per run; a second walk
1281 : /// returns 0xFFFFFFFF immediately (alreadyWalked). The log is a 1024-entry ring (hw agent 2026-10-14).
1282 : EVBTxHistory ReadEVBTxHistory(bool readEntries);
1283 : /// Status line plus, when frozen, the entries in a window around the peer's last-acknowledged sequence.
1284 : std::string FormatEVBTxHistoryText(const EVBTxHistory& history, const std::string& indent, size_t windowEntries = 12);
1285 : void SetEVBRemoteChunkControl(uint32_t value); // 0x917C whole word
1286 : std::vector<uint32_t> ReadEVBStallCounters(); // 0x9210..0x923C then 0x9240..0x9248 (15 values), read back to back
1287 : std::string FormatEVBStallCountersText(const std::string& indent);
1288 : std::string FormatEVBStallCountersDeltaText(const std::vector<uint32_t>& startValues, const std::vector<uint32_t>& endValues, const std::string& indent);
1289 : std::string FormatEVBStallCountersTotalsText(const std::vector<uint64_t>& totals, const std::string& indent); // summed deltas (runs longer than the 17 s wrap)
1290 : uint16_t ReadEVBROCInputWords(std::optional<uint32_t> val = std::nullopt); // 0x9200 [15:0]
1291 : uint16_t ReadEVBSelfTransferWords(std::optional<uint32_t> val = std::nullopt); // 0x9200 [31:16]
1292 : uint16_t ReadEVBDDRFIFOWriteWords(std::optional<uint32_t> val = std::nullopt); // 0x9204 [15:0]
1293 : uint16_t ReadEVBDDRToTXWords(std::optional<uint32_t> val = std::nullopt); // 0x9204 [31:16]
1294 : uint16_t ReadEVBBufferManagerOutputWords(std::optional<uint32_t> val = std::nullopt); // 0x9208 [15:0]
1295 : uint16_t ReadEVBDMAOutputWords(std::optional<uint32_t> val = std::nullopt); // 0x9208 [31:16]
1296 : uint16_t ReadEVBGBERXWords(std::optional<uint32_t> val = std::nullopt); // 0x920C [15:0]
1297 :
1298 : // RX Data Packet Count
1299 : uint32_t ReadRXDataPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1300 : RegisterFormatter FormatRXDataPacketCountLink(DTC_Link_ID const& link);
1301 : DTC_Register GetRXDataPacketCountLinkRegister(DTC_Link_ID const& link);
1302 :
1303 : // EVB Diagnostic RX Packet FIFO
1304 : uint64_t ReadEVBDiagnosticFIFO(std::optional<uint32_t> val = std::nullopt);
1305 : void ClearEVBDiagnosticFIFO();
1306 : // No formatters for FIFO!
1307 :
1308 : // Event Mode Lookup Table
1309 : void SetAllEventModeWords(uint32_t data);
1310 : void SetEventModeWord(uint8_t which, uint32_t data);
1311 : uint32_t ReadEventModeWord(uint8_t which);
1312 :
1313 : // Oscillator Programming (DDR and SERDES)
1314 : bool SetNewOscillatorFrequency(DTC_OscillatorType oscillator, double targetFrequency);
1315 : uint64_t ReadCurrentProgram(DTC_OscillatorType oscillator);
1316 : void WriteCurrentProgram(uint64_t program, DTC_OscillatorType oscillator);
1317 :
1318 : private:
1319 0 : bool NeedToVerifyRegisterWrite_(const CFOandDTC_Register& /*address*/) override { return true; }
1320 : void VerifyRegisterWrite_(const CFOandDTC_Register& address, uint32_t readbackValue, uint32_t dataToWrite) override;
1321 :
1322 : int DecodeHighSpeedDivider_(int input);
1323 0 : int DecodeOutputDivider_(int input) { return input + 1; }
1324 0 : double DecodeRFREQ_(uint64_t input) { return input / 268435456.0; }
1325 : int EncodeHighSpeedDivider_(int input);
1326 : int EncodeOutputDivider_(int input);
1327 0 : uint64_t EncodeRFREQ_(double input) { return static_cast<uint64_t>(input * 268435456) & 0x3FFFFFFFFF; }
1328 : uint64_t CalculateFrequencyForProgramming_(double targetFrequency, double currentFrequency, uint64_t currentProgram);
1329 : uint64_t ReadSERDESOscillatorParameters_();
1330 : uint64_t ReadTimingOscillatorParameters_();
1331 : // uint64_t ReadDDROscillatorParameters_();
1332 : void SetSERDESOscillatorParameters_(uint64_t program);
1333 : void SetTimingOscillatorParameters_(uint64_t program);
1334 : // void SetDDROscillatorParameters_(uint64_t program);
1335 :
1336 : bool WaitForLinkReady_(DTC_Link_ID const& link, size_t interval, double timeout = 2.0 /*seconds*/);
1337 :
1338 : std::unordered_map<uint8_t, std::pair<uint32_t, std::chrono::steady_clock::time_point>> lastPacketCount;
1339 : std::unordered_map<uint8_t, double> lastPacketRate;
1340 :
1341 : protected:
1342 : DTC_SimMode simMode_; ///< Simulation mode
1343 : bool usingDetectorEmulator_{false}; ///< Whether Detector Emulation mode is enabled
1344 : uint16_t dmaSize_; ///< Size of DMAs, in bytes (default 32k)
1345 :
1346 : public:
1347 : std::pair<uint32_t, std::chrono::steady_clock::time_point> getPacketCountInfo(uint8_t dtc) const;
1348 : void updatePacketCount(uint8_t dtc, uint32_t currentCount);
1349 : double getLastPacketRate(uint8_t dtc) const;
1350 :
1351 0 : bool WaitForLinkReady(DTC_Link_ID const& link, size_t interval, double timeout = 2.0) { return WaitForLinkReady_(link, interval, timeout); }
1352 0 : virtual const std::vector<std::function<RegisterFormatter()>>& getFormattedDumpFunctions() override { return formattedDumpFunctions_; }; // pure virtual
1353 0 : virtual const std::vector<std::function<RegisterFormatter()>>& getFormattedSimpleDumpFunctions() override { return formattedSimpleDumpFunctions_; }; // pure virtual
1354 :
1355 : const std::vector<std::function<RegisterFormatter()>> formattedSimpleDumpFunctions_{
1356 0 : [this] { return this->FormatDeviceHash(); }, // mu2e_host_hash
1357 0 : [this] { return this->FormatDeviceTimeAlive(); },
1358 0 : [this] { return this->FormatDTCControl(); },
1359 0 : [this] { return this->FormatJitterAttenuatorCSR(); },
1360 0 : [this] { return this->FormatSERDESPLLLocked(); },
1361 0 : [this] { return this->FormatROCEmulationEnable(); },
1362 0 : [this] { return this->FormatLinkEnable(); },
1363 0 : [this] { return this->FormatCFOLinkError(); },
1364 0 : [this] { return this->FormatCFO40MHzClockMarkerEnables(); },
1365 0 : [this] { return this->FormatRXCDRLockStatus(); },
1366 0 : [this] { return this->FormatSERDESResetDone(); },
1367 0 : [this] { return this->FormatSERDESReset(); },
1368 : };
1369 : const std::vector<std::function<RegisterFormatter()>> formattedROCEmulationFunctions_{
1370 0 : [this] { return this->FormatROCEmulationEnable(); },
1371 0 : [this] { return this->FormatLinkEnable(); },
1372 0 : [this] { return this->FormatRXCDRLockStatus(); },
1373 0 : [this] { return this->FormatROCEmulationNumPacketsLink01(); },
1374 0 : [this] { return this->FormatROCEmulationNumPacketsLink23(); },
1375 0 : [this] { return this->FormatROCEmulationNumPacketsLink45(); },
1376 : };
1377 :
1378 : const std::vector<std::function<RegisterFormatter()>> formattedDumpFunctions_{
1379 0 : [this] { return this->FormatDesignVersion(); },
1380 0 : [this] { return this->FormatDesignDate(); },
1381 0 : [this] { return this->FormatDesignStatus(); },
1382 0 : [this] { return this->FormatVivadoVersion(); },
1383 0 : [this] { return this->FormatFPGATemperature(); },
1384 0 : [this] { return this->FormatFPGAVCCINT(); },
1385 0 : [this] { return this->FormatFPGAVCCAUX(); },
1386 0 : [this] { return this->FormatFPGAVCCBRAM(); },
1387 0 : [this] { return this->FormatFPGAAlarms(); },
1388 0 : [this] { return this->FormatDTCControl(); },
1389 0 : [this] { return this->FormatSERDESPLLLocked(); },
1390 0 : [this] { return this->FormatDMATransferLength(); },
1391 0 : [this] { return this->FormatSERDESLoopbackEnable(); },
1392 0 : [this] { return this->FormatClockOscillatorStatus(); },
1393 0 : [this] { return this->FormatROCEmulationEnable(); },
1394 0 : [this] { return this->FormatLinkEnable(); },
1395 0 : [this] { return this->FormatSERDESReset(); },
1396 0 : [this] { return this->FormatSERDESRXDisparityError(); },
1397 0 : [this] { return this->FormatSERDESRXCharacterNotInTableError(); },
1398 0 : [this] { return this->FormatSERDESUnlockError(); },
1399 0 : [this] { return this->FormatSERDESPLLPowerDown(); },
1400 0 : [this] { return this->FormatSERDESRXStatus(); },
1401 0 : [this] { return this->FormatSERDESResetDone(); },
1402 0 : [this] { return this->FormatRXCDRLockStatus(); },
1403 0 : [this] { return this->FormatDMATimeoutPreset(); },
1404 0 : [this] { return this->FormatROCReplyTimeout(); },
1405 0 : [this] { return this->FormatROCReplyTimeoutError(); },
1406 0 : [this] { return this->FormatEVBLocalParitionIDMACIndex(); },
1407 0 : [this] { return this->FormatEVBClusterInfo(); },
1408 0 : [this] { return this->FormatSERDESOscillatorControl(); },
1409 0 : [this] { return this->FormatSERDESOscillatorParameterLow(); },
1410 0 : [this] { return this->FormatSERDESOscillatorParameterHigh(); },
1411 : // [this] { return this->FormatDDROscillatorFrequency(); },
1412 : // [this] { return this->FormatDDROscillatorControl(); },
1413 : // [this] { return this->FormatDDROscillatorParameterLow(); },
1414 : // [this] { return this->FormatDDROscillatorParameterHigh(); },
1415 0 : [this] { return this->FormatFIFOFullErrorFlag0(); },
1416 0 : [this] { return this->FormatFIFOFullErrorFlag1(); },
1417 0 : [this] { return this->FormatFIFOFullErrorFlag2(); },
1418 0 : [this] { return this->FormatReceivePacketError(); },
1419 0 : [this] { return this->FormatCFOEmulationTimestampLow(); },
1420 0 : [this] { return this->FormatCFOEmulationTimestampHigh(); },
1421 0 : [this] { return this->FormatCFOEmulationEventWindowInterval(); },
1422 0 : [this] { return this->FormatCFOEmulationNumHeartbeats(); },
1423 0 : [this] { return this->FormatROCEmulationNumPacketsLink01(); },
1424 0 : [this] { return this->FormatROCEmulationNumPacketsLink23(); },
1425 0 : [this] { return this->FormatROCEmulationNumPacketsLink45(); },
1426 0 : [this] { return this->FormatCFOEmulationNumNullHeartbeats(); },
1427 0 : [this] { return this->FormatCFOEmulationModeBytes03(); },
1428 0 : [this] { return this->FormatCFOEmulationModeBytes45(); },
1429 : //[this] { return this->FormatCFOEmulationDebugPacketType(); },
1430 0 : [this] { return this->FormatRXPacketCountErrorFlags(); },
1431 0 : [this] { return this->FormatDetectorEmulationDMACount(); },
1432 0 : [this] { return this->FormatDetectorEmulationDMADelayCount(); },
1433 0 : [this] { return this->FormatDetectorEmulationControl0(); },
1434 0 : [this] { return this->FormatDetectorEmulationControl1(); },
1435 0 : [this] { return this->FormatDDRDataLocalStartAddress(); },
1436 0 : [this] { return this->FormatDDRDataLocalEndAddress(); },
1437 0 : [this] { return this->FormatCFOEmulatorInterpacketDelay(); },
1438 0 : [this] { return this->FormatEthernetPayloadSize(); },
1439 0 : [this] { return this->FormatCFOEmulation40MHzMarkerInterval(); },
1440 0 : [this] { return this->FormatCFO40MHzClockMarkerEnables(); },
1441 0 : [this] { return this->FormatROCFinishThreshold(); },
1442 0 : [this] { return this->FormatFireflyTXIICControl(); },
1443 0 : [this] { return this->FormatFireflyTXIICParameterLow(); },
1444 0 : [this] { return this->FormatFireflyTXIICParameterHigh(); },
1445 0 : [this] { return this->FormatFireflyRXIICControl(); },
1446 0 : [this] { return this->FormatFireflyRXIICParameterLow(); },
1447 0 : [this] { return this->FormatFireflyRXIICParameterHigh(); },
1448 0 : [this] { return this->FormatFireflyTXRXIICControl(); },
1449 0 : [this] { return this->FormatFireflyTXRXIICParameterLow(); },
1450 0 : [this] { return this->FormatFireflyTXRXIICParameterHigh(); },
1451 0 : [this] { return this->FormatSERDESTXPRBSControl(); },
1452 0 : [this] { return this->FormatSERDESRXPRBSControl(); },
1453 0 : [this] { return this->FormatEventModeLookupTableControl(); },
1454 0 : [this] { return this->FormatDDRMemoryTestRegister(); },
1455 0 : [this] { return this->FormatSERDESSerialInversionEnable(); },
1456 0 : [this] { return this->FormatJitterAttenuatorCSR(); },
1457 0 : [this] { return this->FormatSFPIICControl(); },
1458 0 : [this] { return this->FormatSFPIICParameterLow(); },
1459 0 : [this] { return this->FormatSFPIICParameterHigh(); },
1460 0 : [this] { return this->FormatEVBSubEventReceiveTimer(); },
1461 0 : [this] { return this->FormatEVBSERDESPRBSControl(); },
1462 0 : [this] { return this->FormatEventBuilderErrorRegister(); },
1463 0 : [this] { return this->FormatSERDESVFIFOError(); },
1464 0 : [this] { return this->FormatPCIVFIFOError(); },
1465 0 : [this] { return this->FormatRocLink0Error(); },
1466 0 : [this] { return this->FormatRocLink1Error(); },
1467 0 : [this] { return this->FormatRocLink2Error(); },
1468 0 : [this] { return this->FormatRocLink3Error(); },
1469 0 : [this] { return this->FormatRocLink4Error(); },
1470 0 : [this] { return this->FormatRocLink5Error(); },
1471 0 : [this] { return this->FormatCFOLinkError(); },
1472 0 : [this] { return this->FormatLinkMuxError(); },
1473 0 : [this] { return this->FormatFireflyCSR(); },
1474 0 : [this] { return this->FormatSFPControlStatus(); },
1475 0 : [this] { return this->FormatRTFHistIdelay(); },
1476 0 : [this] { return this->FormatSoftwareDataRequestLow(); },
1477 0 : [this] { return this->FormatSoftwareDataRequestHigh(); },
1478 0 : [this] { return this->FormatFPGAPROMProgramStatus(); },
1479 0 : [this] { return this->FormatFPGACoreAccess(); },
1480 0 : [this] { return this->FormatSlowOpticalLinkControlStatus(); },
1481 0 : [this] { return this->FormatSERDESRXCRCErrorControl(); },
1482 : };
1483 :
1484 : const std::vector<std::function<RegisterFormatter()>> formattedPerformanceCounterFunctions_{
1485 : // [this] { return this->FormatDDRLinkBufferEmptyFlags0(); },
1486 : // [this] { return this->FormatDDRLinkBufferEmptyFlags1(); },
1487 : // [this] { return this->FormatDDRLinkBufferEmptyFlags2(); },
1488 : // [this] { return this->FormatDDRLinkBufferEmptyFlags3(); },
1489 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags0(); },
1490 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags1(); },
1491 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags2(); },
1492 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags3(); },
1493 : // [this] { return this->FormatDDRLinkBufferFullFlags0(); },
1494 : // [this] { return this->FormatDDRLinkBufferFullFlags1(); },
1495 : // [this] { return this->FormatDDRLinkBufferFullFlags2(); },
1496 : // [this] { return this->FormatDDRLinkBufferFullFlags3(); },
1497 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags0(); },
1498 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags1(); },
1499 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags2(); },
1500 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags3(); },
1501 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags0(); },
1502 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags1(); },
1503 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags2(); },
1504 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags3(); },
1505 : // [this] { return this->FormatDDREventBuilderBufferFullFlags0(); },
1506 : // [this] { return this->FormatDDREventBuilderBufferFullFlags1(); },
1507 : // [this] { return this->FormatDDREventBuilderBufferFullFlags2(); },
1508 : // [this] { return this->FormatDDREventBuilderBufferFullFlags3(); },
1509 0 : [this] { return this->FormatRetransmitRequestCountLink0(); },
1510 0 : [this] { return this->FormatRetransmitRequestCountLink1(); },
1511 0 : [this] { return this->FormatRetransmitRequestCountLink2(); },
1512 0 : [this] { return this->FormatRetransmitRequestCountLink3(); },
1513 0 : [this] { return this->FormatRetransmitRequestCountLink4(); },
1514 0 : [this] { return this->FormatRetransmitRequestCountLink5(); },
1515 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink0(); },
1516 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink1(); },
1517 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink2(); },
1518 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink3(); },
1519 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink4(); },
1520 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink5(); }
1521 :
1522 : };
1523 :
1524 : const std::vector<std::function<RegisterFormatter()>> formattedSERDESErrorFunctions_{
1525 0 : [this] { return this->FormatCFOLinkError(); },
1526 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink0(); },
1527 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink1(); },
1528 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink2(); },
1529 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink3(); },
1530 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink4(); },
1531 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink5(); },
1532 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountCFOLink(); },
1533 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink0(); },
1534 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink1(); },
1535 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink2(); },
1536 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink3(); },
1537 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink4(); },
1538 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink5(); },
1539 0 : [this] { return this->FormatSERDESRXDisparityErrorCountCFOLink(); },
1540 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink0(); },
1541 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink1(); },
1542 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink2(); },
1543 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink3(); },
1544 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink4(); },
1545 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink5(); },
1546 0 : [this] { return this->FormatSERDESRXPRBSErrorCountCFOLink(); },
1547 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink0(); },
1548 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink1(); },
1549 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink2(); },
1550 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink3(); },
1551 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink4(); },
1552 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink5(); },
1553 0 : [this] { return this->FormatSERDESRXCRCErrorCountCFOLink(); },
1554 0 : [this] { return this->FormatEVBSERDESRXPacketErrorCounter(); },
1555 0 : [this] { return this->FormatJitterAttenuatorRecoveredClockLOSCount(); },
1556 0 : [this] { return this->FormatJitterAttenuatorExternalClockLOSCount(); }
1557 :
1558 : };
1559 :
1560 : const std::vector<std::function<RegisterFormatter()>> formattedPacketCounterFunctions_{
1561 : // [this] { return this->FormatMissedCFOPacketCountLink0(); },
1562 : // [this] { return this->FormatMissedCFOPacketCountLink1(); },
1563 : // [this] { return this->FormatMissedCFOPacketCountLink2(); },
1564 : // [this] { return this->FormatMissedCFOPacketCountLink3(); },
1565 : // [this] { return this->FormatMissedCFOPacketCountLink4(); },
1566 : // [this] { return this->FormatMissedCFOPacketCountLink5(); },
1567 : // [this] { return this->FormatLocalFragmentDropCount(); },
1568 : // [this] { return this->FormatOutputBufferFragmentDumpCount(); },
1569 :
1570 0 : [this] { return this->FormatCFOTXClockMarkerCountLink6(); },
1571 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_CFO); },
1572 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_CFO); },
1573 0 : [this] { return this->FormatCFOLinkError(); },
1574 :
1575 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_0); },
1576 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_1); },
1577 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_2); },
1578 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_3); },
1579 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_4); },
1580 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_5); },
1581 :
1582 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_0); },
1583 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_1); },
1584 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_2); },
1585 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_3); },
1586 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_4); },
1587 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_5); },
1588 :
1589 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_0); },
1590 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_1); },
1591 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_2); },
1592 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_3); },
1593 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_4); },
1594 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_5); },
1595 :
1596 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_0); },
1597 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_1); },
1598 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_2); },
1599 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_3); },
1600 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_4); },
1601 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_5); },
1602 :
1603 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_0); },
1604 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_1); },
1605 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_2); },
1606 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_3); },
1607 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_4); },
1608 0 : [this] { return this->FormatTXBlockedHeartbeatCountLink(DTC_Link_5); },
1609 :
1610 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_0); },
1611 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_1); },
1612 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_2); },
1613 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_3); },
1614 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_4); },
1615 0 : [this] { return this->FormatTXNonnullHeartbeatCountLink(DTC_Link_5); },
1616 :
1617 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_0); },
1618 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_1); },
1619 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_2); },
1620 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_3); },
1621 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_4); },
1622 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_5); },
1623 :
1624 0 : [this] { return this->FormatCFOCDCDiag(); },
1625 :
1626 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_0); },
1627 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_1); },
1628 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_2); },
1629 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_3); },
1630 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_4); },
1631 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_5); }
1632 :
1633 : };
1634 :
1635 : const std::vector<std::function<RegisterFormatter()>> formattedHWEventBuildingFunctions_{
1636 :
1637 0 : [this] { return this->FormatEVBLocalParitionIDMACIndex(); },
1638 0 : [this] { return this->FormatEVBClusterInfo(); },
1639 0 : [this] { return this->FormatCFOTXClockMarkerCountLink6(); },
1640 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_CFO); },
1641 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_CFO); },
1642 0 : [this] { return this->FormatCFOLinkError(); },
1643 0 : [this] { return this->FormatEVBPacketControlInfo(); },
1644 0 : [this] { return this->FormatEVBStats(); },
1645 :
1646 : };
1647 : };
1648 : } // namespace DTCLib
1649 :
1650 : #endif // DTC_REGISTERS_H
|
