Line data Source code
1 : #ifndef DTC_REGISTERS_H
2 : #define DTC_REGISTERS_H
3 :
4 : // #include <bitset> // std::bitset
5 : // #include <cstdint> // uint8_t, uint16_t
6 : #include <functional> // std::bind, std::function
7 : #include <vector> // std::vector
8 :
9 : #include "CFOandDTC_Registers.h"
10 : #include "artdaq-core-mu2e/Overlays/DTC_Types/DTC_EVBStatsType.h"
11 :
12 : namespace DTCLib
13 : {
14 : enum DTC_Register : uint16_t
15 : {
16 : DTCLIB_COMMON_REGISTERS, // Moved here all registers in common with CFO
17 :
18 : DTC_Register_ROCEmulationEnable = 0x9110,
19 :
20 : // 0x913C Reserved
21 : DTC_Register_SERDES_RXCDRLockStatus = 0x9140,
22 : DTC_Register_DMATimeoutPreset = 0x9144,
23 : DTC_Register_ROCReplyTimeout = 0x9148,
24 : DTC_Register_ROCReplyTimeoutError = 0x914C,
25 : // 0x9150 Reserved
26 : DTC_Register_EVBPartitionID = 0x9154,
27 : DTC_Register_EVBConfiguration = 0x9158,
28 : DTC_Register_EVBPacketControl = 0x915C,
29 : DTC_Register_EVBStats = 0x9160,
30 : DTC_Register_SERDESClock_IICBusControl = 0x9164,
31 : // DTC_Register_DDRReferenceClockFrequency = 0x9170,
32 : // DTC_Register_DDRClock_IICBusControl = 0x9174,
33 : // DTC_Register_DDRClock_IICBusLow = 0x9178,
34 : // DTC_Register_DDRClock_IICBusHigh = 0x917C,
35 : // Reserved - formerly... DTC_Register_DDRWriteResponseTimer = 0x9180,
36 : DTC_Register_CFOEmulation_LoopbackDelayMeasure = 0x9184,
37 : // Reserved - formerly... DTC_Register_DataPendingTimer = 0x9188,
38 : // 0x918C Reserved
39 : DTC_Register_FIFOFullErrorFlag0 = 0x9190,
40 : DTC_Register_FIFOFullErrorFlag1 = 0x9194,
41 : DTC_Register_FIFOFullErrorFlag2 = 0x9198,
42 : DTC_Register_ReceivePacketError = 0x919C,
43 : DTC_Register_CFOEmulation_TimestampLow = 0x91A0,
44 : DTC_Register_CFOEmulation_TimestampHigh = 0x91A4,
45 : DTC_Register_CFOEmulation_HeartbeatInterval = 0x91A8,
46 : DTC_Register_CFOEmulation_NumHeartbeats = 0x91AC,
47 : DTC_Register_ROCEmulation_NumPacketsLinks10 = 0x91B0,
48 : DTC_Register_ROCEmulation_NumPacketsLinks32 = 0x91B4,
49 : DTC_Register_ROCEmulation_NumPacketsLinks54 = 0x91B8,
50 : DTC_Register_CFOEmulation_NumNullHeartbeats = 0x91BC,
51 : DTC_Register_CFOEmulation_EventMode1 = 0x91C0,
52 : DTC_Register_CFOEmulation_EventMode2 = 0x91C4,
53 : DTC_Register_CFOEventModeRequiredMask = 0x91C8,
54 : DTC_Register_RXPacketCountErrorFlags = 0x91CC,
55 : DTC_Register_DetEmulation_DMACount = 0x91D0,
56 : DTC_Register_DetEmulation_DelayCount = 0x91D4,
57 : DTC_Register_DetEmulation_Control0 = 0x91D8,
58 : DTC_Register_DetEmulation_Control1 = 0x91DC,
59 : DTC_Register_DetEmulation_DataStartAddress = 0x91E0,
60 : DTC_Register_DetEmulation_DataEndAddress = 0x91E4,
61 : DTC_Register_EthernetFramePayloadSize = 0x91EC,
62 : DTC_Register_CFOEmulation_DataRequestDelay = 0x91E8,
63 : DTC_Register_EthernetFrameMaxPayload = 0x91EC,
64 : // 0x91F0 Reserved
65 : DTC_Register_CFOEmulation_40MHzClockMarkerInterval = 0x91F4,
66 : DTC_Register_CFOMarkerEnables = 0x91F8,
67 : DTC_Register_ROCFinishThreshold = 0x91FC,
68 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link0 = 0x9200,
69 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link1 = 0x9204,
70 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link2 = 0x9208,
71 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link3 = 0x920C,
72 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link4 = 0x9210,
73 : // Reserved - formerly... DTC_Register_ReceiveByteCount_Link5 = 0x9214,
74 : // Reserved - formerly... DTC_Register_ReceiveByteCount_CFOLink = 0x9218,
75 : // 0x921C Reserved
76 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link0 = 0x9220,
77 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link1 = 0x9224,
78 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link2 = 0x9228,
79 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link3 = 0x922C,
80 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link4 = 0x9230,
81 : // Reserved - formerly... DTC_Register_ReceivePacketCount_Link5 = 0x9234,
82 : // Reserved - formerly... DTC_Register_ReceivePacketCount_CFOLink = 0x9238,
83 : // 0x923C Reserved
84 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link0 = 0x9240,
85 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link1 = 0x9244,
86 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link2 = 0x9248,
87 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link3 = 0x924C,
88 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link4 = 0x9250,
89 : // Reserved - formerly... DTC_Register_TransmitByteCount_Link5 = 0x9254,
90 : // Reserved - formerly... DTC_Register_TransmitByteCount_CFOLink = 0x9258,
91 : // 0x925C Reserved
92 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link0 = 0x9260,
93 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link1 = 0x9264,
94 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link2 = 0x9268,
95 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link3 = 0x926C,
96 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link4 = 0x9270,
97 : // Reserved - formerly... DTC_Register_TransmitPacketCount_Link5 = 0x9274,
98 : // Reserved - formerly... DTC_Register_TransmitPacketCount_CFOLink = 0x9278,
99 : // 0x927C Reserved
100 : // 0x9280 Reserved
101 : // 0x9290 Reserved
102 : // 0x92A0 Reserved
103 : DTC_Register_TXPRBSControl = 0x92B0,
104 : DTC_Register_RXPRBSControl = 0x92B4,
105 : // 0x92B8 Reserved
106 : // 0x92BC Reserved
107 : DTC_Register_EventModeLookupTableControl = 0x92C0,
108 : // 0x92C4-0x92EC Reserved
109 : DTC_Register_DD3TestRegister = 0x92F0,
110 : // 0x92F4 Reserved
111 : // 0x92F8 Reserved
112 : // 0x92FC Reserved
113 : DTC_Register_SERDESTXRXInvertEnable = 0x9300,
114 : // 0x9304 Reserved
115 : DTC_Register_JitterAttenuatorCSR = 0x9308,
116 : // 0x930C Reserved
117 : // 0x9310 Reserved
118 : DTC_Register_SFP_IICBusControl = 0x9314,
119 : DTC_Register_SFP_IICBusLow = 0x9318,
120 : DTC_Register_SFP_IICBusHigh = 0x931C,
121 : DTC_Register_RetransmitRequestCount_Link0 = 0x9320,
122 : DTC_Register_RetransmitRequestCount_Link1 = 0x9324,
123 : DTC_Register_RetransmitRequestCount_Link2 = 0x9328,
124 : DTC_Register_RetransmitRequestCount_Link3 = 0x932C,
125 : DTC_Register_RetransmitRequestCount_Link4 = 0x9330,
126 : DTC_Register_RetransmitRequestCount_Link5 = 0x9334,
127 : // 0x9338 Reserved
128 : // 0x933C Reserved
129 : DTC_Register_MissedCFOPacketCount_Link0 = 0x9340,
130 : DTC_Register_MissedCFOPacketCount_Link1 = 0x9344,
131 : DTC_Register_MissedCFOPacketCount_Link2 = 0x9348,
132 : DTC_Register_MissedCFOPacketCount_Link3 = 0x934C,
133 : DTC_Register_MissedCFOPacketCount_Link4 = 0x9350,
134 : DTC_Register_MissedCFOPacketCount_Link5 = 0x9354,
135 : // 0x9358 Reserved
136 : // 0x935C Reserved
137 : DTC_Register_LocalFragmentDropCount = 0x9360,
138 : DTC_Register_EVBSubEventReceiveTimerPreset = 0x9364,
139 : DTC_Register_EVBSERDESPRBSControlStatus = 0x9368,
140 : // 0x936C Reserved
141 : DTC_Register_EventBuilderErrorFlags = 0x9370,
142 : DTC_Register_InputBufferErrorFlags = 0x9374,
143 : DTC_Register_OutputBufferErrorFlags = 0x9378,
144 : DTC_Register_Link0ErrorFlags = 0x9380,
145 : DTC_Register_Link1ErrorFlags = 0x9384,
146 : DTC_Register_Link2ErrorFlags = 0x9388,
147 : DTC_Register_Link3ErrorFlags = 0x938C,
148 : DTC_Register_Link4ErrorFlags = 0x9390,
149 : DTC_Register_Link5ErrorFlags = 0x9394,
150 : DTC_Register_CFOLinkErrorFlags = 0x9398,
151 : DTC_Register_LinkMuxErrorFlags = 0x939C,
152 : DTC_Register_SFPControlStatus = 0x93A4,
153 : // 0x93A8 Reserved
154 : // 0x93AC Reserved
155 : DTC_Register_RXCDRUnlockCount_Link0 = 0x93B0,
156 : DTC_Register_RXCDRUnlockCount_Link1 = 0x93B4,
157 : DTC_Register_RXCDRUnlockCount_Link2 = 0x93B8,
158 : DTC_Register_RXCDRUnlockCount_Link3 = 0x93BC,
159 : DTC_Register_RXCDRUnlockCount_Link4 = 0x93C0,
160 : DTC_Register_RXCDRUnlockCount_Link5 = 0x93C4,
161 : DTC_Register_RXCDRUnlockCount_CFOLink = 0x93C8,
162 : DTC_Register_JitterAttenuatorLossOfLockCount = 0x93CC,
163 : DTC_Register_CFOLinkEventStartErrorCount = 0x93D0,
164 : DTC_Register_CFOLink40MHzErrorCount = 0x93D4,
165 : DTC_Register_InputBufferDropCount = 0x93D8,
166 : DTC_Register_OutputBufferDropCount = 0x93DC,
167 : DTC_Register_ROCDCSTimerPreset = 0x93E0,
168 : DTC_Register_DataRequest_Low = 0x93F8,
169 : DTC_Register_DataRequest_High = 0x93FC,
170 : // 0x93E4 - 0x93FC Reserved
171 : DTC_Register_FPGAProgramData = 0x9400,
172 : DTC_Register_FPGAPROMProgramStatus = 0x9404,
173 : DTC_Register_FPGACoreAccess = 0x9408,
174 : // 0x940C Reserved
175 : DTC_Register_SlowOpticalLinksDiag = 0x9410,
176 : DTC_Register_DiagSERDESErrorEnable = 0x9414,
177 : DTC_Register_DiagSERDESPacket0 = 0x9418,
178 : DTC_Register_DiagSERDESPacket1 = 0x941C,
179 : DTC_Register_DiagSERDESPacket2 = 0x9420,
180 : DTC_Register_DiagSERDESPacket3 = 0x9424,
181 : DTC_Register_DiagSERDESPacket4 = 0x9428,
182 : DTC_Register_DiagSERDESPacket5 = 0x942C,
183 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags0 = 0x9430,
184 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags1 = 0x9434,
185 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags2 = 0x9438,
186 : // Reserved - formerly... DTC_Register_DDR3LinkBufferEmptyFlags3 = 0x943C,
187 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags0 = 0x9440,
188 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags1 = 0x9444,
189 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags2 = 0x9448,
190 : // Reserved - formerly... DTC_Register_DDR3LinkBufferHalfFullFlags3 = 0x944C,
191 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags0 = 0x9450,
192 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags1 = 0x9454,
193 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags2 = 0x9458,
194 : // Reserved - formerly... DTC_Register_DDR3LinkBufferFullFlags3 = 0x945C,
195 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags0 = 0x9460,
196 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags1 = 0x9464,
197 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags2 = 0x9468,
198 : // Reserved - formerly... DTC_Register_DDR3EVBBufferEmptyFlags3 = 0x946C,
199 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags0 = 0x9470,
200 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags1 = 0x9474,
201 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags2 = 0x9478,
202 : // Reserved - formerly... DTC_Register_DDR3EVBBufferHalfFullFlags3 = 0x947C,
203 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags0 = 0x9480,
204 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags1 = 0x9484,
205 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags2 = 0x9488,
206 : // Reserved - formerly... DTC_Register_DDR3EVBBufferFullFlags3 = 0x948C,
207 : DTC_Register_DataPendingDiagTimer_Link0 = 0x9490,
208 : DTC_Register_DataPendingDiagTimer_Link1 = 0x9494,
209 : DTC_Register_DataPendingDiagTimer_Link2 = 0x9498,
210 : DTC_Register_DataPendingDiagTimer_Link3 = 0x949C,
211 : DTC_Register_DataPendingDiagTimer_Link4 = 0x94A0,
212 : DTC_Register_DataPendingDiagTimer_Link5 = 0x94A4,
213 : // 0x94A8 Reserved
214 : // 0x94AC Reserved
215 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link0 = 0x94B0,
216 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link1 = 0x94B4,
217 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link2 = 0x94B8,
218 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link3 = 0x94BC,
219 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link4 = 0x94C0,
220 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceTimeoutError_Link5 = 0x94C4,
221 : // 0x94C8 Reserved
222 : // 0x94CC Reserved
223 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link0 = 0x94D0,
224 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link1 = 0x94D4,
225 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link2 = 0x94D8,
226 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link3 = 0x94DC,
227 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link4 = 0x94E0,
228 : // Reserved - formerly... DTC_Register_ROCEmulator_InduceExtraWordError_Link5 = 0x94E4,
229 : // 0x94E8 - 0x94FC Reserved
230 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link0 = 0x9500,
231 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link1 = 0x9504,
232 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link2 = 0x9508,
233 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link3 = 0x950C,
234 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link4 = 0x9510,
235 : DTC_Register_SERDES_CharacterNotInTableErrorCount_Link5 = 0x9514,
236 : DTC_Register_SERDES_CharacterNotInTableErrorCount_CFOLink = 0x9518,
237 : // 0x951C Reserved
238 : DTC_Register_SERDES_RXDisparityErrorCount_Link0 = 0x9520,
239 : DTC_Register_SERDES_RXDisparityErrorCount_Link1 = 0x9524,
240 : DTC_Register_SERDES_RXDisparityErrorCount_Link2 = 0x9528,
241 : DTC_Register_SERDES_RXDisparityErrorCount_Link3 = 0x952C,
242 : DTC_Register_SERDES_RXDisparityErrorCount_Link4 = 0x9530,
243 : DTC_Register_SERDES_RXDisparityErrorCount_Link5 = 0x9534,
244 : DTC_Register_SERDES_RXDisparityErrorCount_CFOLink = 0x9538,
245 : // 0x953C Reserved
246 : DTC_Register_SERDES_RXPRBSErrorCount_Link0 = 0x9540,
247 : DTC_Register_SERDES_RXPRBSErrorCount_Link1 = 0x9544,
248 : DTC_Register_SERDES_RXPRBSErrorCount_Link2 = 0x9548,
249 : DTC_Register_SERDES_RXPRBSErrorCount_Link3 = 0x954C,
250 : DTC_Register_SERDES_RXPRBSErrorCount_Link4 = 0x9550,
251 : DTC_Register_SERDES_RXPRBSErrorCount_Link5 = 0x9554,
252 : DTC_Register_SERDES_RXPRBSErrorCount_CFOLink = 0x9558,
253 : // 0x955C Reserved
254 : DTC_Register_SERDES_RXCRCErrorCount_Link0 = 0x9560,
255 : DTC_Register_SERDES_RXCRCErrorCount_Link1 = 0x9564,
256 : DTC_Register_SERDES_RXCRCErrorCount_Link2 = 0x9568,
257 : DTC_Register_SERDES_RXCRCErrorCount_Link3 = 0x956C,
258 : DTC_Register_SERDES_RXCRCErrorCount_Link4 = 0x9570,
259 : DTC_Register_SERDES_RXCRCErrorCount_Link5 = 0x9574,
260 : DTC_Register_SERDES_RXCRCErrorCount_CFOLink = 0x9578,
261 : DTC_Register_SERDES_RXCRCErrorControl = 0x957C,
262 : // 0x9580 - 0x958C Reserved
263 : DTC_Register_EBVSERDES_RXPacketErrorCount = 0x9590,
264 : // 0x9594 - 0x959C Reserved
265 : DTC_Register_JitterAttenuator_SERDES_RXRecoveredClockLOSCount = 0x95A0,
266 : DTC_Register_JitterAttenuator_SERDES_RXExternalClockLOSCount = 0x95A4,
267 : // 0x9598 - 0x960C Reserved
268 : DTC_Register_ROCEmulator_InterpacketDelay_Link0 = 0x9610,
269 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link1 = 0x9614,
270 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link2 = 0x9618,
271 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link3 = 0x961C,
272 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link4 = 0x9620,
273 : // Reserved - formerly... DTC_Register_ROCEmulator_InterpacketDelay_Link5 = 0x9624,
274 : // 0x9628 Reserved
275 : // 0x962C Reserved
276 : DTC_Register_TXDataRequestPacketCount_Link0 = 0x9630,
277 : DTC_Register_TXDataRequestPacketCount_Link1 = 0x9634,
278 : DTC_Register_TXDataRequestPacketCount_Link2 = 0x9638,
279 : DTC_Register_TXDataRequestPacketCount_Link3 = 0x963C,
280 : DTC_Register_TXDataRequestPacketCount_Link4 = 0x9640,
281 : DTC_Register_TXDataRequestPacketCount_Link5 = 0x9644,
282 : DTC_Register_CFOTXClockMarkerCount_Link6 = 0x9648,
283 : // 0x9648 Reserved
284 : // 0x964C Reserved
285 : DTC_Register_TXHeartbeatPacketCount_Link0 = 0x9650,
286 : DTC_Register_TXHeartbeatPacketCount_Link1 = 0x9654,
287 : DTC_Register_TXHeartbeatPacketCount_Link2 = 0x9658,
288 : DTC_Register_TXHeartbeatPacketCount_Link3 = 0x965C,
289 : DTC_Register_TXHeartbeatPacketCount_Link4 = 0x9660,
290 : DTC_Register_TXHeartbeatPacketCount_Link5 = 0x9664,
291 : DTC_Register_CFOTXHeartbeatPacketCount_Link5 = 0x9668,
292 : // 0x9668 Reserved
293 : // 0x966C Reserved
294 : DTC_Register_RXDataHeaderPacketCount_Link0 = 0x9670,
295 : DTC_Register_RXDataHeaderPacketCount_Link1 = 0x9674,
296 : DTC_Register_RXDataHeaderPacketCount_Link2 = 0x9678,
297 : DTC_Register_RXDataHeaderPacketCount_Link3 = 0x967C,
298 : DTC_Register_RXDataHeaderPacketCount_Link4 = 0x9680,
299 : DTC_Register_RXDataHeaderPacketCount_Link5 = 0x9684,
300 : // 0x9688 Reserved
301 : // 0x968C Reserved
302 : DTC_Register_RXDataPacketCount_Link0 = 0x9690,
303 : DTC_Register_RXDataPacketCount_Link1 = 0x9694,
304 : DTC_Register_RXDataPacketCount_Link2 = 0x9698,
305 : DTC_Register_RXDataPacketCount_Link3 = 0x969C,
306 : DTC_Register_RXDataPacketCount_Link4 = 0x96A0,
307 : DTC_Register_RXDataPacketCount_Link5 = 0x96A4,
308 : // 0x96A8 Reserved
309 : // 0x96AC Reserved
310 : DTC_Register_EVBDiagnosticRXPacket_Low = 0x96B0,
311 : DTC_Register_EVBDiagnosticRXPacket_High = 0x96B4,
312 : DTC_Register_EventModeLookupTableStart = 0xA000,
313 : DTC_Register_EventModeLookupTableEnd = 0xA3FC,
314 :
315 : DTC_Register_RXDataDiagnosticFIFO_Link0 = 0x96D0,
316 : DTC_Register_RXDataDiagnosticFIFO_Link1 = 0x96D4,
317 : DTC_Register_RXDataDiagnosticFIFO_Link2 = 0x96D8,
318 : DTC_Register_RXDataDiagnosticFIFO_Link3 = 0x96DC,
319 : DTC_Register_RXDataDiagnosticFIFO_Link4 = 0x96E0,
320 : DTC_Register_RXDataDiagnosticFIFO_Link5 = 0x96E4,
321 :
322 : DTC_Register_TXDataDiagnosticFIFO_Link0 = 0x96E8,
323 : DTC_Register_TXDataDiagnosticFIFO_Link1 = 0x96EC,
324 : DTC_Register_TXDataDiagnosticFIFO_Link2 = 0x96F0,
325 : DTC_Register_TXDataDiagnosticFIFO_Link3 = 0x96F4,
326 : DTC_Register_TXDataDiagnosticFIFO_Link4 = 0x96F8,
327 : DTC_Register_TXDataDiagnosticFIFO_Link5 = 0x96FC,
328 :
329 : DTC_Register_RXDataDiagnosticFIFO_LinkCFO = 0x9700,
330 : DTC_Register_TXDataDiagnosticFIFO_LinkCFO = 0x9708,
331 :
332 : DTC_Register_TXEventWindowMarkerCount_Link0 = 0xA400,
333 : DTC_Register_TXEventWindowMarkerCount_Link1 = 0xA404,
334 : DTC_Register_TXEventWindowMarkerCount_Link2 = 0xA408,
335 : DTC_Register_TXEventWindowMarkerCount_Link3 = 0xA40C,
336 : DTC_Register_TXEventWindowMarkerCount_Link4 = 0xA410,
337 : DTC_Register_TXEventWindowMarkerCount_Link5 = 0xA414,
338 : DTC_Register_CFOTXEventWindowMarkerCount_Link6 = 0xA418,
339 :
340 : DTC_Register_TXNullHeartbeatCount_Link0 = 0xA440,
341 : DTC_Register_TXNullHeartbeatCount_Link1 = 0xA444,
342 : DTC_Register_TXNullHeartbeatCount_Link2 = 0xA448,
343 : DTC_Register_TXNullHeartbeatCount_Link3 = 0xA44C,
344 : DTC_Register_TXNullHeartbeatCount_Link4 = 0xA450,
345 : DTC_Register_TXNullHeartbeatCount_Link5 = 0xA454,
346 :
347 : DTC_Register_Invalid,
348 : // };
349 : }; // end DTC_Register enum
350 :
351 : /// <summary>
352 : /// The DTC_Registers class represents the DTC Register space, and all the methods necessary to read and write those
353 : /// registers. Each register has, at the very least, a read method, a write method, and a RegisterFormatter method
354 : /// which formats the register value in a human-readable way.
355 : /// </summary>
356 : class DTC_Registers : public CFOandDTC_Registers
357 : {
358 : public:
359 : explicit DTC_Registers(DTC_SimMode mode, int dtc, std::string simFileName, unsigned linkMask = 0x1, std::string expectedDesignVersion = "", bool skipInit = false, const std::string& uid = "");
360 :
361 : virtual ~DTC_Registers();
362 :
363 : //
364 : // DTC Sim Mode Virtual Register
365 : //
366 : /// <summary>
367 : /// Get the current DTC_SimMode of this DTC_Registers object
368 : /// </summary>
369 : /// <returns></returns>
370 0 : DTC_SimMode GetSimMode() const { return simMode_; }
371 :
372 : DTC_SimMode SetSimMode(std::string expectedDesignVersion, DTC_SimMode mode, int dtc, std::string simMemoryFile, unsigned linkMask, bool skipInit = false, const std::string& uid = "");
373 :
374 : //
375 : // Register IO Functions
376 : //
377 :
378 : // Design Status Register
379 : bool ReadDDRInterfaceReset(std::optional<uint32_t> val = std::nullopt);
380 : void SetDDRInterfaceReset(bool reset);
381 : void ResetDDRInterface();
382 : bool ReadDDRAutoCalibrationDone(std::optional<uint32_t> val = std::nullopt);
383 : RegisterFormatter FormatDesignStatus();
384 :
385 : // DTC Control Register
386 : void EnableCFOEmulation(); // B30
387 : void DisableCFOEmulation(); // B30
388 : bool ReadCFOEmulationEnabled(std::optional<uint32_t> val = std::nullopt); // B30
389 : // Bit 29 Reserved
390 : void EnableCFOLoopback(); // B28
391 : void DisableCFOLoopback(); // B28
392 : bool ReadCFOLoopback(std::optional<uint32_t> val = std::nullopt); // B28
393 : void ResetDDRWriteAddress(); // B27
394 : bool ReadResetDDRWriteAddress(std::optional<uint32_t> val = std::nullopt); // B27
395 : void ResetDDRReadAddress(); // B26
396 : bool ReadResetDDRReadAddress(std::optional<uint32_t> val = std::nullopt); // B26
397 : void ResetDDR(); // B25
398 : bool ReadResetDDR(std::optional<uint32_t> val = std::nullopt); // B25
399 : void EnableCFOEmulatorDRP(); // B24
400 : void DisableCFOEmulatorDRP(); // B24
401 : bool ReadCFOEmulatorDRP(std::optional<uint32_t> val = std::nullopt); // B24
402 : void EnableAutogenDRP(); // B23
403 : void DisableAutogenDRP(); // B23
404 : bool ReadAutogenDRP(std::optional<uint32_t> val = std::nullopt); // B23
405 : void EnableSoftwareDRP(); // alias to DisableAutogenDRP()
406 : void DisableSoftwareDRP(); // B23
407 : bool ReadSoftwareDRP(std::optional<uint32_t> val = std::nullopt); // alias to EnableAutogenDRP()
408 : void EnableKillTimeoutROCs(); // B22
409 : void DisableKillTimeoutROCs(); // B22
410 : bool ReadKillTimeoutROCs(std::optional<uint32_t> val = std::nullopt); // B22
411 : virtual void ResetPCIe() override; // B21
412 : bool ReadResetPCIe(std::optional<uint32_t> val = std::nullopt); // B21
413 : // Bit 20 Reserved
414 : void EnableDownLED0(); // B19
415 : void DisableDownLED0(); // B19
416 : bool ReadDownLED0State(std::optional<uint32_t> val = std::nullopt); // B19
417 : void EnableUpLED1(); // B18
418 : void DisableUpLED1(); // B18
419 : bool ReadUpLED1State(std::optional<uint32_t> val = std::nullopt); // B18
420 : void EnableUpLED0(); // B17
421 : void DisableUpLED0(); // B17
422 : bool ReadUpLED0State(std::optional<uint32_t> val = std::nullopt); // B17
423 : void EnableLED6(); // B16
424 : void DisableLED6(); // B16
425 : bool ReadLED6State(std::optional<uint32_t> val = std::nullopt); // B16
426 : void EnableLEDs();
427 : void DisableLEDs();
428 : virtual void FlashLEDs() override;
429 :
430 : void SetCFOEmulationMode(); // B15
431 : void ClearCFOEmulationMode(); // B15
432 : bool ReadCFOEmulationMode(std::optional<uint32_t> val = std::nullopt); // B15
433 : // Bit 14 Reserved
434 : void SetDataFilterEnable(); // B13
435 : void ClearDataFilterEnable(); // B13
436 : bool ReadDataFilterEnable(std::optional<uint32_t> val = std::nullopt); // B13
437 : void SetDRPPrefetchEnable(); // B12
438 : void ClearDRPPrefetchEnable(); // B12
439 : bool ReadDRPPrefetchEnable(std::optional<uint32_t> val = std::nullopt); // B12
440 : void ROCInterfaceSoftReset(); // B11
441 : bool ReadROCInterfaceSoftReset(std::optional<uint32_t> val = std::nullopt); // B11
442 : void EnableDropDataToEmulateEventBuilding(); // B10
443 : void DisableDropDataToEmulateEventBuilding(); // B10
444 : bool ReadDropDataToEmulateEventBuilding(std::optional<uint32_t> val = std::nullopt); // B10
445 : // void SetPunchEnable(); // B9 implemented for CFO and DTC
446 : // void ClearPunchEnable(); // B9 implemented for CFO and DTC
447 : // bool ReadPunchEnable(std::optional<uint32_t> val = std::nullopt); // B9 implemented for CFO and DTC
448 : // void ResetSERDES(); // B8 implemented for CFO and DTC
449 : // bool ReadResetSERDES(std::optional<uint32_t> val = std::nullopt); // B8 implemented for CFO and DTC
450 : void SetExternalCFOSampleEdgeMode(int forceCFOedge); // B6:5
451 : int ReadExternalCFOSampleEdgeMode(std::optional<uint32_t> val); // B6:5
452 : void SetExternalFanoutClockInput(); // B4
453 : void SetInternalFanoutClockInput(); // B4
454 : bool ReadFanoutClockInput(std::optional<uint32_t> val = std::nullopt); // B4
455 : // void RunCFOEmulatorLoopbackTest(); // B3 implemented for CFO and DTC
456 : void EnableDCSReception(); // B2
457 : void DisableDCSReception(); // B2
458 : bool ReadDCSReception(std::optional<uint32_t> val = std::nullopt); // B2
459 : // Bit 1 Reserved
460 : // Bit 0 Reserved
461 : RegisterFormatter FormatDTCControl();
462 :
463 : void SetCFOSamplePermanentOffset(int permanentOffset);
464 : int ReadCFOSamplePermanentOffset(std::optional<uint32_t> val = std::nullopt);
465 :
466 : // DMA Transfer Length Register
467 : void SetTriggerDMATransferLength(uint16_t length);
468 : uint16_t ReadTriggerDMATransferLength(std::optional<uint32_t> val = std::nullopt);
469 : void SetMinDMATransferLength(uint16_t length);
470 : uint16_t ReadMinDMATransferLength(std::optional<uint32_t> val = std::nullopt);
471 : RegisterFormatter FormatDMATransferLength();
472 :
473 : // SERDES Loopback Enable Register
474 : void SetSERDESLoopbackMode(DTC_Link_ID const& link, const DTC_SERDESLoopbackMode& mode);
475 : DTC_SERDESLoopbackMode ReadSERDESLoopback(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
476 : RegisterFormatter FormatSERDESLoopbackEnable();
477 :
478 : // Clock Status Register
479 : bool ReadSERDESOscillatorIICError(std::optional<uint32_t> val = std::nullopt);
480 : bool ReadDDROscillatorIICError(std::optional<uint32_t> val = std::nullopt);
481 : RegisterFormatter FormatClockOscillatorStatus();
482 :
483 : // ROC Emulation Enable Register
484 0 : void EnableROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation);
485 0 : void DisableROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation);
486 : bool ReadROCEmulator(DTC_Link_ID const& link, DTC_ROC_Emulation_Type const& type = DTC_ROC_Emulation_Type::ROC_Internal_Emulation, std::optional<uint32_t> val = std::nullopt);
487 : void SetROCEmulatorMask(uint32_t rocEnableMask);
488 : uint32_t ReadROCEmulatorMask(std::optional<uint32_t> val = std::nullopt);
489 : RegisterFormatter FormatROCEmulationEnable();
490 :
491 : // Link Enable Register
492 : void EnableReceiveCFOLink();
493 : void DisableReceiveCFOLink();
494 : void EnableTransmitCFOLink();
495 : void DisableTransmitCFOLink();
496 : void EnableLink(DTC_Link_ID const& link, const DTC_LinkEnableMode& mode = DTC_LinkEnableMode());
497 : void DisableLink(DTC_Link_ID const& link, const DTC_LinkEnableMode& mode = DTC_LinkEnableMode());
498 : DTC_LinkEnableMode ReadLinkEnabled(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
499 : uint32_t ReadLinkEnabledData();
500 : bool ReadBlockNullHeartbeatsToROC(std::optional<uint32_t> val = std::nullopt);
501 : void SetBlockNullHeartbeatsToROC(bool enable);
502 : bool ReadResequenceNonNullEvents(std::optional<uint32_t> val = std::nullopt);
503 : void SetResequenceNonNullEvents(bool enable);
504 : bool ReadAutoGenDRPPerLink(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
505 : void SetAutoGenDRPPerLink(DTC_Link_ID const& link, bool enable);
506 : RegisterFormatter FormatLinkEnable();
507 :
508 : // SERDES Reset Register
509 : void ResetSERDESTX(DTC_Link_ID const& link, int interval = 100000);
510 : bool ReadResetSERDESTX(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
511 : void ResetSERDESRX(DTC_Link_ID const& link, int interval = 100000);
512 : bool ReadResetSERDESRX(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
513 : void ResetSERDESPLL(const DTC_PLL_ID& pll, int interval = 100000);
514 : bool ReadResetSERDESPLL(const DTC_PLL_ID& pll, std::optional<uint32_t> val = std::nullopt);
515 : void ResetSERDES(DTC_Link_ID const& link, int interval = 100000);
516 : bool ReadResetSERDES(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
517 : RegisterFormatter FormatSERDESReset();
518 :
519 : // Link Diagnostic FIFOs
520 : DTCLib::RegisterFormatter FormatRXDiagFifo(DTC_Link_ID const& link);
521 : DTCLib::RegisterFormatter FormatTXDiagFifo(DTC_Link_ID const& link);
522 :
523 : // SERDES RX Disparity Error Register
524 : DTC_SERDESRXDisparityError ReadSERDESRXDisparityError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
525 : RegisterFormatter FormatSERDESRXDisparityError();
526 :
527 : // SERDES Character Not In Table Error Register
528 : DTC_CharacterNotInTableError ReadSERDESRXCharacterNotInTableError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
529 : RegisterFormatter FormatSERDESRXCharacterNotInTableError();
530 :
531 : // SERDES Unlock Error Register
532 : bool ReadSERDESCDRUnlockError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
533 : bool ReadSERDESPLLUnlockError(const DTC_PLL_ID& pll, std::optional<uint32_t> val = std::nullopt);
534 : RegisterFormatter FormatSERDESUnlockError();
535 :
536 : // SERDES PLL Locked Register
537 : bool ReadSERDESPLLLocked(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
538 : RegisterFormatter FormatSERDESPLLLocked();
539 :
540 : // SERDES PLL Power Down
541 : void EnableSERDESPLL(DTC_Link_ID const& link);
542 : void DisableSERDESPLL(DTC_Link_ID const& link);
543 : bool ReadSERDESPLLPowerDown(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
544 : RegisterFormatter FormatSERDESPLLPowerDown();
545 :
546 : // SERDES RX Status Register
547 : DTC_RXStatus ReadSERDESRXStatus(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
548 : RegisterFormatter FormatSERDESRXStatus();
549 :
550 : // SERDES Reset Done Register
551 : bool ReadResetRXFSMSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
552 : bool ReadResetRXSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
553 : bool ReadResetTXFSMSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
554 : bool ReadResetTXSERDESDone(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
555 : RegisterFormatter FormatSERDESResetDone();
556 :
557 : // SERDES CDR Lock Register
558 : bool ReadSERDESRXCDRLock(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
559 : RegisterFormatter FormatRXCDRLockStatus();
560 :
561 : // DMA Timeout Preset Regsiter
562 : void SetDMATimeoutPreset(uint32_t preset);
563 : uint32_t ReadDMATimeoutPreset(std::optional<uint32_t> val = std::nullopt);
564 : RegisterFormatter FormatDMATimeoutPreset();
565 :
566 : // ROC Timeout (Header Packet to All Packets Received) Preset Register
567 : void SetROCTimeoutPreset(uint32_t preset);
568 : uint32_t ReadROCTimeoutPreset(std::optional<uint32_t> val = std::nullopt);
569 : RegisterFormatter FormatROCReplyTimeout();
570 :
571 : // ROC Timeout Error Register
572 : void ClearROCTimeoutError(DTC_Link_ID const& link);
573 : bool ReadROCTimeoutError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
574 : RegisterFormatter FormatROCReplyTimeoutError();
575 :
576 : //----------------- Hardware Event Building configuration -----------------------
577 :
578 : // EVB Network Partition ID / EVB Network Local MAC Index Register
579 : void SetEVBInfo(uint8_t dtcid, uint8_t mode, uint8_t partitionId, uint8_t macByte);
580 : void SetDTCID(uint8_t dtcid);
581 : uint8_t ReadDTCID(std::optional<uint32_t> val = std::nullopt);
582 : void SetEVBMode(uint8_t mode);
583 : uint8_t ReadEVBMode(std::optional<uint32_t> val = std::nullopt);
584 : void SetEVBLocalParitionID(uint8_t id);
585 : uint8_t ReadEVBLocalParitionID(std::optional<uint32_t> val = std::nullopt);
586 : void SetEVBLocalMACAddress(uint8_t macByte);
587 : uint8_t ReadEVBLocalMACAddress(std::optional<uint32_t> val = std::nullopt);
588 : RegisterFormatter FormatEVBLocalParitionIDMACIndex();
589 :
590 : // EVB Cluster Config
591 : void SetEVBClusterInfo(uint16_t deadTime, uint8_t baseDTCAddress, uint8_t numOfDTCs);
592 : void SetEVBDeadTime(uint16_t deadTime);
593 : uint16_t ReadEVBDeadTime(std::optional<uint32_t> val = std::nullopt);
594 : void SetEVBStartNode(uint8_t node);
595 : uint8_t ReadEVBStartNode(std::optional<uint32_t> val = std::nullopt);
596 : void SetEVBNumberOfDestinationNodes(uint8_t number);
597 : uint8_t ReadEVBNumberOfDestinationNodes(std::optional<uint32_t> val = std::nullopt);
598 : RegisterFormatter FormatEVBClusterInfo();
599 :
600 : // EVB Packet Control
601 : void SetEVBPacketControlInfo(uint16_t idlePacketWordCount, uint8_t interpacketGap, uint8_t loopbackCalibratedOffset);
602 : uint16_t ReadEVBIdlePacketWordCount(std::optional<uint32_t> val = std::nullopt);
603 : uint8_t ReadEVBInterpacketGap(std::optional<uint32_t> val = std::nullopt);
604 : uint8_t ReadEVBLoopbackCalibratedOffset(std::optional<uint32_t> val = std::nullopt);
605 : RegisterFormatter FormatEVBPacketControlInfo();
606 :
607 : // EVB Stats
608 : uint32_t ReadEVBStats(DTC_EVBStatsType type, uint8_t dtc_mac, std::optional<uint32_t> val = std::nullopt);
609 : RegisterFormatter FormatEVBStats(DTC_EVBStatsType type = DTC_EVBStatsType::DTC_EVBStatsType_All);
610 : std::chrono::time_point<std::chrono::steady_clock> EVB_startDataTime, EVB_endDataTime;
611 :
612 : //----------------- end Hardware Event Building configuration -----------------------
613 :
614 : // SERDES Oscillator Registers
615 : bool ReadSERDESOscillatorIICInterfaceReset(std::optional<uint32_t> val = std::nullopt);
616 : void ResetSERDESOscillatorIICInterface();
617 :
618 : DTC_SerdesClockSpeed ReadSERDESOscillatorClock(std::optional<uint32_t> val = std::nullopt);
619 : void SetSERDESOscillatorClock(DTC_SerdesClockSpeed speed);
620 : void SetTimingOscillatorClock(uint32_t freq);
621 : RegisterFormatter FormatSERDESOscillatorControl();
622 :
623 : // FIFO Full Error Flags Registers
624 : void ClearFIFOFullErrorFlags(DTC_Link_ID const& link);
625 : DTC_FIFOFullErrorFlags ReadFIFOFullErrorFlags(DTC_Link_ID const& link, std::optional<uint32_t> val0 = std::nullopt, std::optional<uint32_t> val1 = std::nullopt, std::optional<uint32_t> val2 = std::nullopt);
626 : RegisterFormatter FormatFIFOFullErrorFlag0();
627 : RegisterFormatter FormatFIFOFullErrorFlag1();
628 : RegisterFormatter FormatFIFOFullErrorFlag2();
629 :
630 : // Receive Packet Error Register
631 : void ClearPacketError(DTC_Link_ID const& link);
632 : bool ReadPacketError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
633 : void ClearPacketCRCError(DTC_Link_ID const& link);
634 : bool ReadPacketCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
635 : RegisterFormatter FormatReceivePacketError();
636 :
637 : // CFO Emulation Timestamp Registers
638 : void SetCFOEmulationTimestamp(const DTC_EventWindowTag& ts);
639 : DTC_EventWindowTag ReadCFOEmulationTimestamp(std::optional<uint32_t> val = std::nullopt);
640 : RegisterFormatter FormatCFOEmulationTimestampLow();
641 : RegisterFormatter FormatCFOEmulationTimestampHigh();
642 :
643 : // CFO Emulation Heartbeat Interval Regsister
644 : void SetCFOEmulationEventWindowInterval(uint32_t interval);
645 : uint32_t ReadCFOEmulationEventWindowInterval(std::optional<uint32_t> val = std::nullopt);
646 : RegisterFormatter FormatCFOEmulationEventWindowInterval();
647 :
648 : // CFO Emulation Number of Heartbeats Register
649 : void SetCFOEmulationNumHeartbeats(uint32_t numHeartbeats);
650 : uint32_t ReadCFOEmulationNumHeartbeats(std::optional<uint32_t> val = std::nullopt);
651 : RegisterFormatter FormatCFOEmulationNumHeartbeats();
652 :
653 : // CFO Emulation Number of Packets Registers
654 : void SetROCEmulationNumPackets(DTC_Link_ID const& link, uint16_t numPackets);
655 : uint16_t ReadROCEmulationNumPackets(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
656 : RegisterFormatter FormatROCEmulationNumPacketsLink01();
657 : RegisterFormatter FormatROCEmulationNumPacketsLink23();
658 : RegisterFormatter FormatROCEmulationNumPacketsLink45();
659 :
660 : // CFO Emulation Loopback Delay Measure
661 : uint32_t ReadCFOEmulationLoopbackDelayMeasure(std::optional<uint32_t> val = std::nullopt);
662 : RegisterFormatter FormatCFOEmulationLoopbackDelayMeasure();
663 :
664 : // CFO Emulation Number of Null Heartbeats Register
665 : void SetCFOEmulationNumNullHeartbeats(const uint32_t& count);
666 : uint32_t ReadCFOEmulationNumNullHeartbeats(std::optional<uint32_t> val = std::nullopt);
667 : RegisterFormatter FormatCFOEmulationNumNullHeartbeats();
668 :
669 : // CFO Event Mode Required Mask (required bits in event mode for CFO emulation to send a heartbeat. 1 uses them)
670 : // The bits that are required. If a mask-bit is 0, it's accepted anyway.
671 : // If a mask-bit is 1, then the eventMode-bit also needs to be 1 to be accepted.
672 : void SetCFOEventModeRequiredMask(const uint32_t& mask);
673 : uint32_t ReadCFOEventModeRequiredMask(std::optional<uint32_t> val = std::nullopt);
674 : RegisterFormatter FormatCFOEventModeRequiredMask();
675 :
676 : // CFO Emulation Event Mode Bytes Registers
677 : void SetCFOEmulationEventMode(const uint64_t& eventMode);
678 : uint64_t ReadCFOEmulationEventMode();
679 : void SetCFOEmulationModeByte(const uint8_t& byteNum, uint8_t data);
680 : uint8_t ReadCFOEmulationModeByte(const uint8_t& byteNum, std::optional<uint32_t> val = std::nullopt);
681 : RegisterFormatter FormatCFOEmulationModeBytes03();
682 : RegisterFormatter FormatCFOEmulationModeBytes45();
683 :
684 : // CFO Emulation Debug Packet Type Register
685 : // void EnableDebugPacketMode();
686 : // void DisableDebugPacketMode();
687 : // bool ReadDebugPacketMode(std::optional<uint32_t> val = std::nullopt);
688 : // void SetCFOEmulationDebugType(DTC_DebugType type);
689 : // DTC_DebugType ReadCFOEmulationDebugType(std::optional<uint32_t> val = std::nullopt);
690 : // RegisterFormatter FormatCFOEmulationDebugPacketType();
691 :
692 : // RX Packet Count Error Flags Register
693 : bool ReadRXPacketCountErrorFlags(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
694 : void ClearRXPacketCountErrorFlags(DTC_Link_ID const& link);
695 : void ClearRXPacketCountErrorFlags();
696 : RegisterFormatter FormatRXPacketCountErrorFlags();
697 :
698 : // Detector Emulation DMA Count Register
699 : void SetDetectorEmulationDMACount(uint32_t count);
700 : uint32_t ReadDetectorEmulationDMACount(std::optional<uint32_t> val = std::nullopt);
701 : RegisterFormatter FormatDetectorEmulationDMACount();
702 :
703 : // Detector Emulation DMA Delay Count Register
704 : void SetDetectorEmulationDMADelayCount(uint32_t count);
705 : uint32_t ReadDetectorEmulationDMADelayCount(std::optional<uint32_t> val = std::nullopt);
706 : RegisterFormatter FormatDetectorEmulationDMADelayCount();
707 :
708 : // Detector Emulation Control Registers
709 : void EnableDetectorEmulatorMode();
710 : void DisableDetectorEmulatorMode();
711 : bool ReadDetectorEmulatorMode(std::optional<uint32_t> val = std::nullopt);
712 : void EnableDetectorEmulator();
713 : void DisableDetectorEmulator();
714 : bool ReadDetectorEmulatorEnable(std::optional<uint32_t> val = std::nullopt);
715 : bool ReadDetectorEmulatorEnableClear(std::optional<uint32_t> val = std::nullopt);
716 : /// <summary>
717 : /// Return the current value of the "Detector Emulator In Use" virtual register
718 : /// </summary>
719 : /// <returns>Whether the DTC Detector Emulator has been set up</returns>
720 0 : bool IsDetectorEmulatorInUse() const { return usingDetectorEmulator_; }
721 : /// <summary>
722 : /// Set the "Detector Emulator In Use" virtual register to true
723 : /// </summary>
724 0 : void SetDetectorEmulatorInUse()
725 : {
726 : #ifndef __CLING__
727 0 : TLOG(TLVL_WARNING) << "DTC_Registers::SetDetectorEmulatorInUse: Enabling Detector Emulator!";
728 : #endif
729 0 : usingDetectorEmulator_ = true;
730 0 : }
731 : void ClearDetectorEmulatorInUse();
732 : RegisterFormatter FormatDetectorEmulationControl0();
733 : RegisterFormatter FormatDetectorEmulationControl1();
734 :
735 : // DDR Event Data Local Start Address Register
736 : void SetDDRDataLocalStartAddress(uint32_t address);
737 : uint32_t ReadDDRDataLocalStartAddress(std::optional<uint32_t> val = std::nullopt);
738 : RegisterFormatter FormatDDRDataLocalStartAddress();
739 :
740 : // DDR Event Data Local End Address Register
741 : void SetDDRDataLocalEndAddress(uint32_t address);
742 : uint32_t ReadDDRDataLocalEndAddress(std::optional<uint32_t> val = std::nullopt);
743 : RegisterFormatter FormatDDRDataLocalEndAddress();
744 :
745 : // CFO Emulator Data Request Interpacket Delay
746 : uint32_t ReadCFOEmulatorInterpacketDelay(std::optional<uint32_t> val = std::nullopt);
747 : RegisterFormatter FormatCFOEmulatorInterpacketDelay();
748 :
749 : // Ethernet Frame Payload Max Size
750 : uint32_t ReadEthernetPayloadSize(std::optional<uint32_t> val = std::nullopt);
751 : void SetEthernetPayloadSize(uint32_t size);
752 : RegisterFormatter FormatEthernetPayloadSize();
753 :
754 : // CFO Emulation 40 MHz Clock Marker Interval
755 : uint32_t ReadCFOEmulation40MHzMarkerInterval(std::optional<uint32_t> val = std::nullopt);
756 : void SetCFOEmulation40MHzMarkerInterval(uint32_t interval);
757 : RegisterFormatter FormatCFOEmulation40MHzMarkerInterval();
758 :
759 : // CFO Emulation Marker Enables
760 : // bool ReadCFOEmulationEventStartMarkerEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
761 : // void SetCFOEmulationEventStartMarkerEnable(DTC_Link_ID const& link, bool enable);
762 : bool ReadCFO40MHzClockMarkerEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
763 : void SetCFO40MHzClockMarkerEnable(DTC_Link_ID const& link, bool enable);
764 : RegisterFormatter FormatCFO40MHzClockMarkerEnables();
765 :
766 : // ROC Finish Threshold Register
767 : uint8_t ReadROCCommaLimit(std::optional<uint32_t> val = std::nullopt);
768 : void SetROCCommaLimit(uint8_t limit);
769 : RegisterFormatter FormatROCFinishThreshold();
770 :
771 : // SERDES TX PRBS Control
772 : bool ReadTXPRBSForceError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
773 : void SetTXPRBSForceError(DTC_Link_ID const& link);
774 : void ClearTXPRBSForceError(DTC_Link_ID const& link);
775 : DTC_PRBSMode ReadTXPRBSMode(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
776 : void SetTXPRBSMode(DTC_Link_ID const& link, DTC_PRBSMode mode);
777 : RegisterFormatter FormatSERDESTXPRBSControl();
778 :
779 : // SERDES RX PRBS Control
780 : bool ReadRXPRBSError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
781 : DTC_PRBSMode ReadRXPRBSMode(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
782 : void SetRXPRBSMode(DTC_Link_ID const& link, DTC_PRBSMode mode);
783 : RegisterFormatter FormatSERDESRXPRBSControl();
784 :
785 : // DTC Mode Lookup
786 : bool ReadEventModeTableEnable(std::optional<uint32_t> val = std::nullopt);
787 : void SetEventModeTableEnable();
788 : void ClearEventModeTableEnable();
789 : uint8_t ReadEventModeLookupByteSelect(std::optional<uint32_t> val = std::nullopt);
790 : void SetEventModeLookupByteSelect(uint8_t byte);
791 : RegisterFormatter FormatEventModeLookupTableControl();
792 :
793 : // DDR Memory Test Register
794 : bool ReadDDRMemoryTestComplete(std::optional<uint32_t> val = std::nullopt);
795 : bool ReadDDRMemoryTestError(std::optional<uint32_t> val = std::nullopt);
796 : void ClearDDRMemoryTestError();
797 : RegisterFormatter FormatDDRMemoryTestRegister();
798 :
799 : // SERDES Serial Inversion Enable Register
800 : bool ReadInvertSERDESRXInput(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
801 : void SetInvertSERDESRXInput(DTC_Link_ID const& link, bool invert);
802 : bool ReadInvertSERDESTXOutput(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
803 : void SetInvertSERDESTXOutput(DTC_Link_ID const& link, bool invert);
804 : RegisterFormatter FormatSERDESSerialInversionEnable();
805 :
806 : // Jitter Attenuator CSR Register
807 : virtual std::bitset<2> ReadJitterAttenuatorSelect(std::optional<uint32_t> val = std::nullopt) override;
808 : virtual void SetJitterAttenuatorSelect(std::bitset<2> data, bool alsoResetJA = false) override;
809 : virtual bool ReadJitterAttenuatorReset(std::optional<uint32_t> val = std::nullopt) override;
810 : virtual bool ReadJitterAttenuatorLocked(std::optional<uint32_t> val = std::nullopt) override;
811 : virtual void ResetJitterAttenuator() override;
812 : virtual RegisterFormatter FormatJitterAttenuatorCSR() override;
813 :
814 : // void ConfigureJitterAttenuator();
815 :
816 : // SFP IIC Registers
817 : bool ReadSFPIICInterfaceReset(std::optional<uint32_t> val = std::nullopt);
818 : void ResetSFPIICInterface();
819 : void WriteSFPIICInterface(uint8_t device, uint8_t address, uint8_t data);
820 : uint8_t ReadSFPIICInterface(uint8_t device, uint8_t address);
821 : RegisterFormatter FormatSFPIICControl();
822 : RegisterFormatter FormatSFPIICParameterLow();
823 : RegisterFormatter FormatSFPIICParameterHigh();
824 :
825 : // Retransmit Request Count Registers
826 : uint32_t ReadRetransmitRequestCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
827 : void ClearRetransmitRequestCount(DTC_Link_ID const& link);
828 : RegisterFormatter FormatRetransmitRequestCountLink0();
829 : RegisterFormatter FormatRetransmitRequestCountLink1();
830 : RegisterFormatter FormatRetransmitRequestCountLink2();
831 : RegisterFormatter FormatRetransmitRequestCountLink3();
832 : RegisterFormatter FormatRetransmitRequestCountLink4();
833 : RegisterFormatter FormatRetransmitRequestCountLink5();
834 :
835 : // Missed CFO Packet Count Registers
836 : uint32_t ReadMissedCFOPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
837 : void ClearMissedCFOPacketCount(DTC_Link_ID const& link);
838 : RegisterFormatter FormatMissedCFOPacketCountLink0();
839 : RegisterFormatter FormatMissedCFOPacketCountLink1();
840 : RegisterFormatter FormatMissedCFOPacketCountLink2();
841 : RegisterFormatter FormatMissedCFOPacketCountLink3();
842 : RegisterFormatter FormatMissedCFOPacketCountLink4();
843 : RegisterFormatter FormatMissedCFOPacketCountLink5();
844 :
845 : // Local Fragment Drop Count Register
846 : uint32_t ReadLocalFragmentDropCount(std::optional<uint32_t> val = std::nullopt);
847 : void ClearLocalFragmentDropCount();
848 : RegisterFormatter FormatLocalFragmentDropCount();
849 :
850 : // EVB SubEvent Receive Timer Preset
851 : uint32_t ReadEVBSubEventReceiveTimer(std::optional<uint32_t> val = std::nullopt);
852 : void SetEVBSubEventReceiveTimer(uint32_t timer);
853 : RegisterFormatter FormatEVBSubEventReceiveTimer();
854 :
855 : // EVB SERDES PRBS Control / Status Register
856 : bool ReadEVBSERDESPRBSErrorFlag(std::optional<uint32_t> val = std::nullopt);
857 : uint8_t ReadEVBSERDESTXPRBSSEL(std::optional<uint32_t> val = std::nullopt);
858 : void SetEVBSERDESTXPRBSSEL(uint8_t byte);
859 : uint8_t ReadEVBSERDESRXPRBSSEL(std::optional<uint32_t> val = std::nullopt);
860 : void SetEVBSERDESRXPRBSSEL(uint8_t byte);
861 : bool ReadEVBSERDESPRBSForceError(std::optional<uint32_t> val = std::nullopt);
862 : void SetEVBSERDESPRBSForceError(bool flag);
863 : void ToggleEVBSERDESPRBSForceError();
864 : bool ReadEVBSERDESPRBSReset(std::optional<uint32_t> val = std::nullopt);
865 : void SetEVBSERDESPRBSReset(bool flag);
866 : void ToggleEVBSERDESPRBSReset();
867 : RegisterFormatter FormatEVBSERDESPRBSControl();
868 :
869 : // Event Builder Error Register
870 : bool ReadEventBuilder_SubEventReceiverFlagsBufferError(std::optional<uint32_t> val = std::nullopt);
871 : bool ReadEventBuilder_EthernetInputFIFOFull(std::optional<uint32_t> val = std::nullopt);
872 : bool ReadEventBuilder_LinkError(std::optional<uint32_t> val = std::nullopt);
873 : bool ReadEventBuilder_TXPacketError(std::optional<uint32_t> val = std::nullopt);
874 : bool ReadEventBuilder_LocalDataPointerFIFOQueueError(std::optional<uint32_t> val = std::nullopt);
875 : bool ReadEventBuilder_TransmitDMAByteCountFIFOFull(std::optional<uint32_t> val = std::nullopt);
876 : RegisterFormatter FormatEventBuilderErrorRegister();
877 :
878 : // SERDES VFIFO Error Register
879 : bool ReadSERDESVFIFO_EgressFIFOFull(std::optional<uint32_t> val = std::nullopt);
880 : bool ReadSERDESVFIFO_IngressFIFOFull(std::optional<uint32_t> val = std::nullopt);
881 : bool ReadSERDESVFIFO_EventByteCountTotalError(std::optional<uint32_t> val = std::nullopt);
882 : bool ReadSERDESVFIFO_LastWordWrittenTimeoutError(std::optional<uint32_t> val = std::nullopt);
883 : bool ReadSERDESVFIFO_FragmentCountError(std::optional<uint32_t> val = std::nullopt);
884 : bool ReadSERDESVFIFO_DDRFullError(std::optional<uint32_t> val = std::nullopt);
885 : RegisterFormatter FormatSERDESVFIFOError();
886 :
887 : // PCI VFIFO Error Register
888 : bool ReadPCIVFIFO_DDRFull(std::optional<uint32_t> val = std::nullopt);
889 : bool ReadPCIVFIFO_MemoryMappedWriteCompleteFIFOFull(std::optional<uint32_t> val = std::nullopt);
890 : bool ReadPCIVFIFO_PCIWriteEventFIFOFull(std::optional<uint32_t> val = std::nullopt);
891 : bool ReadPCIVFIFO_LocalDataPointerFIFOFull(std::optional<uint32_t> val = std::nullopt);
892 : bool ReadPCIVFIFO_EgressFIFOFull(std::optional<uint32_t> val = std::nullopt);
893 : bool ReadPCIVFIFO_RXBufferSelectFIFOFull(std::optional<uint32_t> val = std::nullopt);
894 : bool ReadPCIVFIFO_IngressFIFOFull(std::optional<uint32_t> val = std::nullopt);
895 : bool ReadPCIVFIFO_EventByteCountTotalError(std::optional<uint32_t> val = std::nullopt);
896 : RegisterFormatter FormatPCIVFIFOError();
897 :
898 : // ROC Link Error Registers
899 : bool ReadROCLink_ROCDataRequestSyncError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
900 : bool ReadROCLink_RXPacketCountError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
901 : bool ReadROCLink_RXPacketError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
902 : bool ReadROCLink_RXPacketCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
903 : bool ReadROCLink_DataPendingTimeoutError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
904 : bool ReadROCLink_ReceiveDataPacketCountError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
905 : RegisterFormatter FormatRocLink0Error();
906 : RegisterFormatter FormatRocLink1Error();
907 : RegisterFormatter FormatRocLink2Error();
908 : RegisterFormatter FormatRocLink3Error();
909 : RegisterFormatter FormatRocLink4Error();
910 : RegisterFormatter FormatRocLink5Error();
911 :
912 : // CFO Link Error Register
913 : RegisterFormatter FormatCFOLinkError();
914 :
915 : // Link Mux Error Register
916 : bool ReadDCSMuxDecodeError(std::optional<uint32_t> val = std::nullopt);
917 : bool ReadDataMuxDecodeError(std::optional<uint32_t> val = std::nullopt);
918 : RegisterFormatter FormatLinkMuxError();
919 :
920 : // SFP Control Status Register
921 : bool ReadSFPPresent(std::optional<uint32_t> val = std::nullopt);
922 : bool ReadSFPLOS(std::optional<uint32_t> val = std::nullopt);
923 : bool ReadSFPTXFault(std::optional<uint32_t> val = std::nullopt);
924 : void EnableSFPRateSelect();
925 : void DisableSFPRateSelect();
926 : bool ReadSFPRateSelect(std::optional<uint32_t> val = std::nullopt);
927 : void DisableSFPTX();
928 : void EnableSFPTX();
929 : bool ReadSFPTXDisable(std::optional<uint32_t> val = std::nullopt);
930 : RegisterFormatter FormatSFPControlStatus();
931 :
932 : // RX CDR Unlock Count Registers
933 : uint32_t ReadRXCDRUnlockCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
934 : void ClearRXCDRUnlockCount(DTC_Link_ID const& link);
935 : RegisterFormatter FormatRXCDRUnlockCountLink0();
936 : RegisterFormatter FormatRXCDRUnlockCountLink1();
937 : RegisterFormatter FormatRXCDRUnlockCountLink2();
938 : RegisterFormatter FormatRXCDRUnlockCountLink3();
939 : RegisterFormatter FormatRXCDRUnlockCountLink4();
940 : RegisterFormatter FormatRXCDRUnlockCountLink5();
941 : RegisterFormatter FormatRXCDRUnlockCountCFOLink();
942 :
943 : // RX Jitter Attenuator Unlock Count Register
944 : uint32_t ReadJitterAttenuatorUnlockCount(std::optional<uint32_t> val = std::nullopt);
945 : void ClearJitterAttenuatorUnlockCount();
946 : RegisterFormatter FormatJitterAttenuatorUnlockCount();
947 :
948 : // RX CFO Link Event Start Character Error Count Register
949 : uint32_t ReadRXCFOLinkEventStartCharacterErrorCount(std::optional<uint32_t> val = std::nullopt);
950 : void ClearRXCFOLinkEventStartCharacterErrorCount();
951 : RegisterFormatter FormatRXCFOLinkEventStartCharacterErrorCount();
952 :
953 : // RX CFO Link 40MHz Clock Character Error Count Register
954 : uint32_t ReadRXCFOLink40MHzCharacterErrorCount(std::optional<uint32_t> val = std::nullopt);
955 : void ClearRXCFOLink40MHzCharacterErrorCount();
956 : RegisterFormatter FormatRXCFOLink40MHzCharacterErrorCount();
957 :
958 : // Input Buffer Fragment Dump Count
959 : uint32_t ReadInputBufferFragmentDumpCount(std::optional<uint32_t> val = std::nullopt);
960 : void ClearInputBufferFragmentDumpCount();
961 : RegisterFormatter FormatInputBufferFragmentDumpCount();
962 :
963 : // Output Buffer Fragment Dump Count
964 : uint32_t ReadOutputBufferFragmentDumpCount(std::optional<uint32_t> val = std::nullopt);
965 : void ClearOutputBufferFragmentDumpCount();
966 : RegisterFormatter FormatOutputBufferFragmentDumpCount();
967 :
968 : // ROC DCS Response Timer Preset
969 : uint32_t ReadROCDCSResponseTimer(std::optional<uint32_t> val = std::nullopt);
970 : void SetROCDCSResponseTimer(uint32_t timer);
971 : RegisterFormatter FormatROCDCSResponseTimerPreset();
972 :
973 : // Software DataRequests
974 : void SetSoftwareDataRequest(const DTC_EventWindowTag& ts);
975 : DTC_EventWindowTag ReadSoftwareDataRequest(std::optional<uint32_t> val = std::nullopt);
976 : RegisterFormatter FormatSoftwareDataRequestLow();
977 : RegisterFormatter FormatSoftwareDataRequestHigh();
978 :
979 : // FPGA PROM Program Data Register
980 :
981 : // FPGA PROM Program Status Register
982 : bool ReadFPGAPROMProgramFIFOFull(std::optional<uint32_t> val = std::nullopt);
983 : bool ReadFPGAPROMReady(std::optional<uint32_t> val = std::nullopt);
984 : RegisterFormatter FormatFPGAPROMProgramStatus();
985 :
986 : // FPGA Core Access Register
987 : void ReloadFPGAFirmware();
988 : bool ReadFPGACoreAccessFIFOFull(std::optional<uint32_t> val = std::nullopt);
989 : bool ReadFPGACoreAccessFIFOEmpty(std::optional<uint32_t> val = std::nullopt);
990 : RegisterFormatter FormatFPGACoreAccess();
991 :
992 : // Slow Optical Links Control/Status Register
993 : bool ReadRXOKErrorSlowOpticalLink3(std::optional<uint32_t> val = std::nullopt);
994 : bool ReadRXOKErrorSlowOpticalLink2(std::optional<uint32_t> val = std::nullopt);
995 : bool ReadRXOKErrorSlowOpticalLink1(std::optional<uint32_t> val = std::nullopt);
996 : bool ReadRXOKErrorSlowOpticalLink0(std::optional<uint32_t> val = std::nullopt);
997 : bool ReadLatchedSpareSMAInputOKError(std::optional<uint32_t> val = std::nullopt);
998 : void ClearLatchedSpareSMAInputOKError();
999 : bool ReadLatchedEventMarkerSMAInputOKError(std::optional<uint32_t> val = std::nullopt);
1000 : void ClearLatchedEventMarkerSMASMAInputOKError();
1001 : bool ReadLatchedRXOKErrorSlowOpticalLink3(std::optional<uint32_t> val = std::nullopt);
1002 : void ClearLatchedRXOKErrorSlowOpticalLink3();
1003 : bool ReadLatchedRXOKErrorSlowOpticalLink2(std::optional<uint32_t> val = std::nullopt);
1004 : void ClearLatchedRXOKErrorSlowOpticalLink2();
1005 : bool ReadLatchedRXOKErrorSlowOpticalLink1(std::optional<uint32_t> val = std::nullopt);
1006 : void ClearLatchedRXOKErrorSlowOpticalLink1();
1007 : bool ReadLatchedRXOKErrorSlowOpticalLink0(std::optional<uint32_t> val = std::nullopt);
1008 : void ClearLatchedRXOKErrorSlowOpticalLink0();
1009 : RegisterFormatter FormatSlowOpticalLinkControlStatus();
1010 :
1011 : // Diagnostic SERDES Induce Error Enable Register
1012 : bool ReadSERDESInduceErrorEnable(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1013 : void EnableSERDESInduceError(DTC_Link_ID const& link);
1014 : void DisableSERDESInduceError(DTC_Link_ID const& link);
1015 : RegisterFormatter FormatSERDESInduceErrorEnable();
1016 :
1017 : // Diagnostic SERDES Incude Error Link Registers
1018 : uint32_t ReadSERDESInduceErrorSequenceNumber(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1019 : void SetSERDESInduceErrorSequenceNumber(DTC_Link_ID const& link, uint32_t sequence);
1020 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink0();
1021 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink1();
1022 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink2();
1023 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink3();
1024 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink4();
1025 : RegisterFormatter FormatSERDESInduceErrorSequenceNumberLink5();
1026 :
1027 : // // DDR Memory Flags Registers
1028 : // DTC_DDRFlags ReadDDRFlags(uint8_t buffer_id);
1029 : // std::bitset<128> ReadDDRLinkBufferFullFlags();
1030 : // std::bitset<128> ReadDDRLinkBufferEmptyFlags();
1031 : // std::bitset<128> ReadDDRLinkBufferHalfFullFlags();
1032 : // std::bitset<128> ReadDDREventBuilderBufferFullFlags();
1033 : // std::bitset<128> ReadDDREventBuilderBufferEmptyFlags();
1034 : // std::bitset<128> ReadDDREventBuilderBufferHalfFullFlags();
1035 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags0();
1036 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags1();
1037 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags2();
1038 : // RegisterFormatter FormatDDRLinkBufferEmptyFlags3();
1039 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags0();
1040 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags1();
1041 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags2();
1042 : // RegisterFormatter FormatDDRLinkBufferHalfFullFlags3();
1043 : // RegisterFormatter FormatDDRLinkBufferFullFlags0();
1044 : // RegisterFormatter FormatDDRLinkBufferFullFlags1();
1045 : // RegisterFormatter FormatDDRLinkBufferFullFlags2();
1046 : // RegisterFormatter FormatDDRLinkBufferFullFlags3();
1047 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags0();
1048 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags1();
1049 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags2();
1050 : // RegisterFormatter FormatDDREventBuilderBufferEmptyFlags3();
1051 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags0();
1052 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags1();
1053 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags2();
1054 : // RegisterFormatter FormatDDREventBuilderBufferHalfFullFlags3();
1055 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags0();
1056 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags1();
1057 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags2();
1058 : // RegisterFormatter FormatDDREventBuilderBufferFullFlags3();
1059 :
1060 : // Data Pending Diagnostic Timer Registers
1061 : uint32_t ReadDataPendingDiagnosticTimer(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1062 : void ResetDataPendingDiagnosticTimerFIFO(DTC_Link_ID const& link);
1063 : RegisterFormatter FormatDataPendingDiagnosticTimerLink0();
1064 : RegisterFormatter FormatDataPendingDiagnosticTimerLink1();
1065 : RegisterFormatter FormatDataPendingDiagnosticTimerLink2();
1066 : RegisterFormatter FormatDataPendingDiagnosticTimerLink3();
1067 : RegisterFormatter FormatDataPendingDiagnosticTimerLink4();
1068 : RegisterFormatter FormatDataPendingDiagnosticTimerLink5();
1069 :
1070 : // SERDES CNIT Error Count
1071 : uint32_t ReadSERDESCharacterNotInTableErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1072 : void ClearSERDESCharacterNotInTableErrorCount(DTC_Link_ID const& link);
1073 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink0();
1074 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink1();
1075 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink2();
1076 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink3();
1077 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink4();
1078 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountLink5();
1079 : RegisterFormatter FormatSERDESCharacterNotInTableErrorCountCFOLink();
1080 :
1081 : // SERDES RX Disparity Error Count
1082 : uint32_t ReadSERDESRXDisparityErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1083 : void ClearSERDESRXDisparityErrorCount(DTC_Link_ID const& link);
1084 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink0();
1085 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink1();
1086 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink2();
1087 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink3();
1088 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink4();
1089 : RegisterFormatter FormatSERDESRXDisparityErrorCountLink5();
1090 : RegisterFormatter FormatSERDESRXDisparityErrorCountCFOLink();
1091 :
1092 : // SERDES RX PRBS Error Count
1093 : uint32_t ReadSERDESRXPRBSErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1094 : void ClearSERDESRXPRBSErrorCount(DTC_Link_ID const& link);
1095 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink0();
1096 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink1();
1097 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink2();
1098 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink3();
1099 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink4();
1100 : RegisterFormatter FormatSERDESRXPRBSErrorCountLink5();
1101 : RegisterFormatter FormatSERDESRXPRBSErrorCountCFOLink();
1102 :
1103 : // SERDES RX CRC Error Count
1104 : uint32_t ReadSERDESRXCRCErrorCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1105 : void ClearSERDESRXCRCErrorCount(DTC_Link_ID const& link);
1106 : RegisterFormatter FormatSERDESRXCRCErrorCountLink0();
1107 : RegisterFormatter FormatSERDESRXCRCErrorCountLink1();
1108 : RegisterFormatter FormatSERDESRXCRCErrorCountLink2();
1109 : RegisterFormatter FormatSERDESRXCRCErrorCountLink3();
1110 : RegisterFormatter FormatSERDESRXCRCErrorCountLink4();
1111 : RegisterFormatter FormatSERDESRXCRCErrorCountLink5();
1112 : RegisterFormatter FormatSERDESRXCRCErrorCountCFOLink();
1113 :
1114 : // SERDES RX CRC Error Control
1115 : bool ReadEnableInduceSERDESRXCRCError(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1116 : void EnableInduceSERDESRXCRCError(DTC_Link_ID const& link);
1117 : void DisableInduceSERDESRXCRCError(DTC_Link_ID const& link);
1118 : RegisterFormatter FormatSERDESRXCRCErrorControl();
1119 :
1120 : uint32_t ReadEVBSERDESRXPacketErrorCounter(std::optional<uint32_t> val = std::nullopt);
1121 : void ClearEVBSERDESRXPacketErrorCounter();
1122 : RegisterFormatter FormatEVBSERDESRXPacketErrorCounter();
1123 :
1124 : // Jitter Attenuator SERDES RX Recovered Clock LOS Counter
1125 : uint32_t ReadJitterAttenuatorRecoveredClockLOSCount(std::optional<uint32_t> val = std::nullopt);
1126 : void ClearJitterAttenuatorRecoeveredClockLOSCount();
1127 : RegisterFormatter FormatJitterAttenuatorRecoveredClockLOSCount();
1128 :
1129 : // Jitter Attenuator SERDES RX External Clock LOS Counter
1130 : uint32_t ReadJitterAttenuatorExternalClockLOSCount(std::optional<uint32_t> val = std::nullopt);
1131 : void ClearJitterAttenuatorExternalClockLOSCount();
1132 : RegisterFormatter FormatJitterAttenuatorExternalClockLOSCount();
1133 :
1134 : // ROC Emulator Interpacket Delay
1135 : uint32_t ReadROCEmulatorInterpacketDelay(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1136 : void SetROCEmulatorInterpacketDelay(DTC_Link_ID const& link, uint32_t delay);
1137 : RegisterFormatter FormatROCEmulatorInterpacketDelayLink0();
1138 :
1139 : // TX Data Request Packet Count
1140 : uint32_t ReadTXDataRequestPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1141 : RegisterFormatter FormatTXDataRequestPacketCountLink(DTC_Link_ID const& link);
1142 : DTC_Register GetTXDataRequestPacketCountLinkRegister(DTC_Link_ID const& link);
1143 :
1144 : RegisterFormatter FormatCFOTXClockMarkerCountLink6();
1145 : uint32_t ReadCFOTXClockMarkerCountLink6(std::optional<uint32_t> val = std::nullopt);
1146 :
1147 : // TX Heartbeat Packet Count
1148 : uint32_t ReadTXHeartbeatPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1149 : RegisterFormatter FormatTXHeartbeatPacketCountLink(DTC_Link_ID const& link);
1150 : DTC_Register GetTXHeartbeatPacketCountLinkRegister(DTC_Link_ID const& link);
1151 :
1152 : // TX Data Request Packet Count
1153 : uint32_t ReadTXEventWindowMarkerCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1154 : RegisterFormatter FormatTXEventWindowMarkerCountLink(DTC_Link_ID const& link);
1155 : DTC_Register GetTXEventWindowMarkerCountLinkRegister(DTC_Link_ID const& link);
1156 :
1157 : // TX Null Heartbeat Packet Count
1158 : uint32_t ReadTXNullHeartbeatCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1159 : RegisterFormatter FormatTXNullHeartbeatCountLink(DTC_Link_ID const& link);
1160 : DTC_Register GetTXNullHeartbeatCountLinkRegister(DTC_Link_ID const& link);
1161 :
1162 : // RX Data Header Packet Count
1163 : uint32_t ReadRXDataHeaderPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1164 : RegisterFormatter FormatRXDataHeaderPacketCountLink(DTC_Link_ID const& link);
1165 : DTC_Register GetRXDataHeaderPacketCountLinkRegister(DTC_Link_ID const& link);
1166 :
1167 : // RX Data Packet Count
1168 : uint32_t ReadRXDataPacketCount(DTC_Link_ID const& link, std::optional<uint32_t> val = std::nullopt);
1169 : RegisterFormatter FormatRXDataPacketCountLink(DTC_Link_ID const& link);
1170 : DTC_Register GetRXDataPacketCountLinkRegister(DTC_Link_ID const& link);
1171 :
1172 : // EVB Diagnostic RX Packet FIFO
1173 : uint64_t ReadEVBDiagnosticFIFO(std::optional<uint32_t> val = std::nullopt);
1174 : void ClearEVBDiagnosticFIFO();
1175 : // No formatters for FIFO!
1176 :
1177 : // Event Mode Lookup Table
1178 : void SetAllEventModeWords(uint32_t data);
1179 : void SetEventModeWord(uint8_t which, uint32_t data);
1180 : uint32_t ReadEventModeWord(uint8_t which);
1181 :
1182 : // Oscillator Programming (DDR and SERDES)
1183 : bool SetNewOscillatorFrequency(DTC_OscillatorType oscillator, double targetFrequency);
1184 : uint64_t ReadCurrentProgram(DTC_OscillatorType oscillator);
1185 : void WriteCurrentProgram(uint64_t program, DTC_OscillatorType oscillator);
1186 :
1187 : private:
1188 0 : bool NeedToVerifyRegisterWrite_(const CFOandDTC_Register& /*address*/) override { return true; }
1189 : void VerifyRegisterWrite_(const CFOandDTC_Register& address, uint32_t readbackValue, uint32_t dataToWrite) override;
1190 :
1191 : int DecodeHighSpeedDivider_(int input);
1192 0 : int DecodeOutputDivider_(int input) { return input + 1; }
1193 0 : double DecodeRFREQ_(uint64_t input) { return input / 268435456.0; }
1194 : int EncodeHighSpeedDivider_(int input);
1195 : int EncodeOutputDivider_(int input);
1196 0 : uint64_t EncodeRFREQ_(double input) { return static_cast<uint64_t>(input * 268435456) & 0x3FFFFFFFFF; }
1197 : uint64_t CalculateFrequencyForProgramming_(double targetFrequency, double currentFrequency, uint64_t currentProgram);
1198 : uint64_t ReadSERDESOscillatorParameters_();
1199 : uint64_t ReadTimingOscillatorParameters_();
1200 : // uint64_t ReadDDROscillatorParameters_();
1201 : void SetSERDESOscillatorParameters_(uint64_t program);
1202 : void SetTimingOscillatorParameters_(uint64_t program);
1203 : // void SetDDROscillatorParameters_(uint64_t program);
1204 :
1205 : bool WaitForLinkReady_(DTC_Link_ID const& link, size_t interval, double timeout = 2.0 /*seconds*/);
1206 :
1207 : std::unordered_map<uint8_t, std::pair<uint32_t, std::chrono::steady_clock::time_point>> lastPacketCount;
1208 : std::unordered_map<uint8_t, double> lastPacketRate;
1209 :
1210 : protected:
1211 : DTC_SimMode simMode_; ///< Simulation mode
1212 : bool usingDetectorEmulator_{false}; ///< Whether Detector Emulation mode is enabled
1213 : uint16_t dmaSize_; ///< Size of DMAs, in bytes (default 32k)
1214 :
1215 : public:
1216 : std::pair<uint32_t, std::chrono::steady_clock::time_point> getPacketCountInfo(uint8_t dtc) const;
1217 : void updatePacketCount(uint8_t dtc, uint32_t currentCount);
1218 : double getLastPacketRate(uint8_t dtc) const;
1219 :
1220 0 : bool WaitForLinkReady(DTC_Link_ID const& link, size_t interval, double timeout = 2.0) { return WaitForLinkReady_(link, interval, timeout); }
1221 0 : virtual const std::vector<std::function<RegisterFormatter()>>& getFormattedDumpFunctions() override { return formattedDumpFunctions_; }; // pure virtual
1222 0 : virtual const std::vector<std::function<RegisterFormatter()>>& getFormattedSimpleDumpFunctions() override { return formattedSimpleDumpFunctions_; }; // pure virtual
1223 :
1224 : const std::vector<std::function<RegisterFormatter()>> formattedSimpleDumpFunctions_{
1225 0 : [this] { return this->FormatDeviceHash(); }, // mu2e_host_hash
1226 0 : [this] { return this->FormatDeviceTimeAlive(); },
1227 0 : [this] { return this->FormatDTCControl(); },
1228 0 : [this] { return this->FormatJitterAttenuatorCSR(); },
1229 0 : [this] { return this->FormatSERDESPLLLocked(); },
1230 0 : [this] { return this->FormatROCEmulationEnable(); },
1231 0 : [this] { return this->FormatLinkEnable(); },
1232 0 : [this] { return this->FormatCFOLinkError(); },
1233 0 : [this] { return this->FormatCFO40MHzClockMarkerEnables(); },
1234 0 : [this] { return this->FormatRXCDRLockStatus(); },
1235 0 : [this] { return this->FormatSERDESResetDone(); },
1236 0 : [this] { return this->FormatSERDESReset(); },
1237 : };
1238 : const std::vector<std::function<RegisterFormatter()>> formattedROCEmulationFunctions_{
1239 0 : [this] { return this->FormatROCEmulationEnable(); },
1240 0 : [this] { return this->FormatLinkEnable(); },
1241 0 : [this] { return this->FormatRXCDRLockStatus(); },
1242 0 : [this] { return this->FormatROCEmulationNumPacketsLink01(); },
1243 0 : [this] { return this->FormatROCEmulationNumPacketsLink23(); },
1244 0 : [this] { return this->FormatROCEmulationNumPacketsLink45(); },
1245 : };
1246 :
1247 : const std::vector<std::function<RegisterFormatter()>> formattedDumpFunctions_{
1248 0 : [this] { return this->FormatDesignVersion(); },
1249 0 : [this] { return this->FormatDesignDate(); },
1250 0 : [this] { return this->FormatDesignStatus(); },
1251 0 : [this] { return this->FormatVivadoVersion(); },
1252 0 : [this] { return this->FormatFPGATemperature(); },
1253 0 : [this] { return this->FormatFPGAVCCINT(); },
1254 0 : [this] { return this->FormatFPGAVCCAUX(); },
1255 0 : [this] { return this->FormatFPGAVCCBRAM(); },
1256 0 : [this] { return this->FormatFPGAAlarms(); },
1257 0 : [this] { return this->FormatDTCControl(); },
1258 0 : [this] { return this->FormatSERDESPLLLocked(); },
1259 0 : [this] { return this->FormatDMATransferLength(); },
1260 0 : [this] { return this->FormatSERDESLoopbackEnable(); },
1261 0 : [this] { return this->FormatClockOscillatorStatus(); },
1262 0 : [this] { return this->FormatROCEmulationEnable(); },
1263 0 : [this] { return this->FormatLinkEnable(); },
1264 0 : [this] { return this->FormatSERDESReset(); },
1265 0 : [this] { return this->FormatSERDESRXDisparityError(); },
1266 0 : [this] { return this->FormatSERDESRXCharacterNotInTableError(); },
1267 0 : [this] { return this->FormatSERDESUnlockError(); },
1268 0 : [this] { return this->FormatSERDESPLLPowerDown(); },
1269 0 : [this] { return this->FormatSERDESRXStatus(); },
1270 0 : [this] { return this->FormatSERDESResetDone(); },
1271 0 : [this] { return this->FormatRXCDRLockStatus(); },
1272 0 : [this] { return this->FormatDMATimeoutPreset(); },
1273 0 : [this] { return this->FormatROCReplyTimeout(); },
1274 0 : [this] { return this->FormatROCReplyTimeoutError(); },
1275 0 : [this] { return this->FormatEVBLocalParitionIDMACIndex(); },
1276 0 : [this] { return this->FormatEVBClusterInfo(); },
1277 0 : [this] { return this->FormatSERDESOscillatorControl(); },
1278 0 : [this] { return this->FormatSERDESOscillatorParameterLow(); },
1279 0 : [this] { return this->FormatSERDESOscillatorParameterHigh(); },
1280 : // [this] { return this->FormatDDROscillatorFrequency(); },
1281 : // [this] { return this->FormatDDROscillatorControl(); },
1282 : // [this] { return this->FormatDDROscillatorParameterLow(); },
1283 : // [this] { return this->FormatDDROscillatorParameterHigh(); },
1284 0 : [this] { return this->FormatFIFOFullErrorFlag0(); },
1285 0 : [this] { return this->FormatFIFOFullErrorFlag1(); },
1286 0 : [this] { return this->FormatFIFOFullErrorFlag2(); },
1287 0 : [this] { return this->FormatReceivePacketError(); },
1288 0 : [this] { return this->FormatCFOEmulationTimestampLow(); },
1289 0 : [this] { return this->FormatCFOEmulationTimestampHigh(); },
1290 0 : [this] { return this->FormatCFOEmulationEventWindowInterval(); },
1291 0 : [this] { return this->FormatCFOEmulationNumHeartbeats(); },
1292 0 : [this] { return this->FormatROCEmulationNumPacketsLink01(); },
1293 0 : [this] { return this->FormatROCEmulationNumPacketsLink23(); },
1294 0 : [this] { return this->FormatROCEmulationNumPacketsLink45(); },
1295 0 : [this] { return this->FormatCFOEmulationNumNullHeartbeats(); },
1296 0 : [this] { return this->FormatCFOEmulationModeBytes03(); },
1297 0 : [this] { return this->FormatCFOEmulationModeBytes45(); },
1298 : //[this] { return this->FormatCFOEmulationDebugPacketType(); },
1299 0 : [this] { return this->FormatRXPacketCountErrorFlags(); },
1300 0 : [this] { return this->FormatDetectorEmulationDMACount(); },
1301 0 : [this] { return this->FormatDetectorEmulationDMADelayCount(); },
1302 0 : [this] { return this->FormatDetectorEmulationControl0(); },
1303 0 : [this] { return this->FormatDetectorEmulationControl1(); },
1304 0 : [this] { return this->FormatDDRDataLocalStartAddress(); },
1305 0 : [this] { return this->FormatDDRDataLocalEndAddress(); },
1306 0 : [this] { return this->FormatCFOEmulatorInterpacketDelay(); },
1307 0 : [this] { return this->FormatEthernetPayloadSize(); },
1308 0 : [this] { return this->FormatCFOEmulation40MHzMarkerInterval(); },
1309 0 : [this] { return this->FormatCFO40MHzClockMarkerEnables(); },
1310 0 : [this] { return this->FormatROCFinishThreshold(); },
1311 0 : [this] { return this->FormatFireflyTXIICControl(); },
1312 0 : [this] { return this->FormatFireflyTXIICParameterLow(); },
1313 0 : [this] { return this->FormatFireflyTXIICParameterHigh(); },
1314 0 : [this] { return this->FormatFireflyRXIICControl(); },
1315 0 : [this] { return this->FormatFireflyRXIICParameterLow(); },
1316 0 : [this] { return this->FormatFireflyRXIICParameterHigh(); },
1317 0 : [this] { return this->FormatFireflyTXRXIICControl(); },
1318 0 : [this] { return this->FormatFireflyTXRXIICParameterLow(); },
1319 0 : [this] { return this->FormatFireflyTXRXIICParameterHigh(); },
1320 0 : [this] { return this->FormatSERDESTXPRBSControl(); },
1321 0 : [this] { return this->FormatSERDESRXPRBSControl(); },
1322 0 : [this] { return this->FormatEventModeLookupTableControl(); },
1323 0 : [this] { return this->FormatDDRMemoryTestRegister(); },
1324 0 : [this] { return this->FormatSERDESSerialInversionEnable(); },
1325 0 : [this] { return this->FormatJitterAttenuatorCSR(); },
1326 0 : [this] { return this->FormatSFPIICControl(); },
1327 0 : [this] { return this->FormatSFPIICParameterLow(); },
1328 0 : [this] { return this->FormatSFPIICParameterHigh(); },
1329 0 : [this] { return this->FormatEVBSubEventReceiveTimer(); },
1330 0 : [this] { return this->FormatEVBSERDESPRBSControl(); },
1331 0 : [this] { return this->FormatEventBuilderErrorRegister(); },
1332 0 : [this] { return this->FormatSERDESVFIFOError(); },
1333 0 : [this] { return this->FormatPCIVFIFOError(); },
1334 0 : [this] { return this->FormatRocLink0Error(); },
1335 0 : [this] { return this->FormatRocLink1Error(); },
1336 0 : [this] { return this->FormatRocLink2Error(); },
1337 0 : [this] { return this->FormatRocLink3Error(); },
1338 0 : [this] { return this->FormatRocLink4Error(); },
1339 0 : [this] { return this->FormatRocLink5Error(); },
1340 0 : [this] { return this->FormatCFOLinkError(); },
1341 0 : [this] { return this->FormatLinkMuxError(); },
1342 0 : [this] { return this->FormatFireflyCSR(); },
1343 0 : [this] { return this->FormatSFPControlStatus(); },
1344 : // [this] { return this->FormatROCDCSResponseTimerPreset(); },
1345 0 : [this] { return this->FormatSoftwareDataRequestLow(); },
1346 0 : [this] { return this->FormatSoftwareDataRequestHigh(); },
1347 0 : [this] { return this->FormatFPGAPROMProgramStatus(); },
1348 0 : [this] { return this->FormatFPGACoreAccess(); },
1349 0 : [this] { return this->FormatSlowOpticalLinkControlStatus(); },
1350 0 : [this] { return this->FormatSERDESRXCRCErrorControl(); },
1351 : };
1352 :
1353 : const std::vector<std::function<RegisterFormatter()>> formattedPerformanceCounterFunctions_{
1354 : // [this] { return this->FormatDDRLinkBufferEmptyFlags0(); },
1355 : // [this] { return this->FormatDDRLinkBufferEmptyFlags1(); },
1356 : // [this] { return this->FormatDDRLinkBufferEmptyFlags2(); },
1357 : // [this] { return this->FormatDDRLinkBufferEmptyFlags3(); },
1358 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags0(); },
1359 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags1(); },
1360 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags2(); },
1361 : // [this] { return this->FormatDDRLinkBufferHalfFullFlags3(); },
1362 : // [this] { return this->FormatDDRLinkBufferFullFlags0(); },
1363 : // [this] { return this->FormatDDRLinkBufferFullFlags1(); },
1364 : // [this] { return this->FormatDDRLinkBufferFullFlags2(); },
1365 : // [this] { return this->FormatDDRLinkBufferFullFlags3(); },
1366 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags0(); },
1367 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags1(); },
1368 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags2(); },
1369 : // [this] { return this->FormatDDREventBuilderBufferEmptyFlags3(); },
1370 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags0(); },
1371 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags1(); },
1372 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags2(); },
1373 : // [this] { return this->FormatDDREventBuilderBufferHalfFullFlags3(); },
1374 : // [this] { return this->FormatDDREventBuilderBufferFullFlags0(); },
1375 : // [this] { return this->FormatDDREventBuilderBufferFullFlags1(); },
1376 : // [this] { return this->FormatDDREventBuilderBufferFullFlags2(); },
1377 : // [this] { return this->FormatDDREventBuilderBufferFullFlags3(); },
1378 0 : [this] { return this->FormatRetransmitRequestCountLink0(); },
1379 0 : [this] { return this->FormatRetransmitRequestCountLink1(); },
1380 0 : [this] { return this->FormatRetransmitRequestCountLink2(); },
1381 0 : [this] { return this->FormatRetransmitRequestCountLink3(); },
1382 0 : [this] { return this->FormatRetransmitRequestCountLink4(); },
1383 0 : [this] { return this->FormatRetransmitRequestCountLink5(); },
1384 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink0(); },
1385 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink1(); },
1386 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink2(); },
1387 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink3(); },
1388 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink4(); },
1389 0 : [this] { return this->FormatDataPendingDiagnosticTimerLink5(); }
1390 :
1391 : };
1392 :
1393 : const std::vector<std::function<RegisterFormatter()>> formattedSERDESErrorFunctions_{
1394 0 : [this] { return this->FormatCFOLinkError(); },
1395 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink0(); },
1396 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink1(); },
1397 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink2(); },
1398 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink3(); },
1399 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink4(); },
1400 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountLink5(); },
1401 0 : [this] { return this->FormatSERDESCharacterNotInTableErrorCountCFOLink(); },
1402 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink0(); },
1403 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink1(); },
1404 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink2(); },
1405 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink3(); },
1406 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink4(); },
1407 0 : [this] { return this->FormatSERDESRXDisparityErrorCountLink5(); },
1408 0 : [this] { return this->FormatSERDESRXDisparityErrorCountCFOLink(); },
1409 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink0(); },
1410 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink1(); },
1411 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink2(); },
1412 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink3(); },
1413 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink4(); },
1414 0 : [this] { return this->FormatSERDESRXPRBSErrorCountLink5(); },
1415 0 : [this] { return this->FormatSERDESRXPRBSErrorCountCFOLink(); },
1416 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink0(); },
1417 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink1(); },
1418 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink2(); },
1419 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink3(); },
1420 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink4(); },
1421 0 : [this] { return this->FormatSERDESRXCRCErrorCountLink5(); },
1422 0 : [this] { return this->FormatSERDESRXCRCErrorCountCFOLink(); },
1423 0 : [this] { return this->FormatEVBSERDESRXPacketErrorCounter(); },
1424 0 : [this] { return this->FormatJitterAttenuatorRecoveredClockLOSCount(); },
1425 0 : [this] { return this->FormatJitterAttenuatorExternalClockLOSCount(); }
1426 :
1427 : };
1428 :
1429 : const std::vector<std::function<RegisterFormatter()>> formattedPacketCounterFunctions_{
1430 : // [this] { return this->FormatMissedCFOPacketCountLink0(); },
1431 : // [this] { return this->FormatMissedCFOPacketCountLink1(); },
1432 : // [this] { return this->FormatMissedCFOPacketCountLink2(); },
1433 : // [this] { return this->FormatMissedCFOPacketCountLink3(); },
1434 : // [this] { return this->FormatMissedCFOPacketCountLink4(); },
1435 : // [this] { return this->FormatMissedCFOPacketCountLink5(); },
1436 : // [this] { return this->FormatLocalFragmentDropCount(); },
1437 : // [this] { return this->FormatOutputBufferFragmentDumpCount(); },
1438 :
1439 0 : [this] { return this->FormatCFOTXClockMarkerCountLink6(); },
1440 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_CFO); },
1441 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_CFO); },
1442 0 : [this] { return this->FormatCFOLinkError(); },
1443 :
1444 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_0); },
1445 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_1); },
1446 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_2); },
1447 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_3); },
1448 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_4); },
1449 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_5); },
1450 :
1451 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_0); },
1452 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_1); },
1453 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_2); },
1454 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_3); },
1455 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_4); },
1456 0 : [this] { return this->FormatTXDataRequestPacketCountLink(DTC_Link_5); },
1457 :
1458 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_0); },
1459 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_1); },
1460 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_2); },
1461 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_3); },
1462 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_4); },
1463 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_5); },
1464 :
1465 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_0); },
1466 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_1); },
1467 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_2); },
1468 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_3); },
1469 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_4); },
1470 0 : [this] { return this->FormatTXNullHeartbeatCountLink(DTC_Link_5); },
1471 :
1472 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_0); },
1473 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_1); },
1474 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_2); },
1475 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_3); },
1476 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_4); },
1477 0 : [this] { return this->FormatRXDataHeaderPacketCountLink(DTC_Link_5); },
1478 :
1479 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_0); },
1480 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_1); },
1481 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_2); },
1482 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_3); },
1483 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_4); },
1484 0 : [this] { return this->FormatRXDataPacketCountLink(DTC_Link_5); }
1485 :
1486 : };
1487 :
1488 : const std::vector<std::function<RegisterFormatter()>> formattedHWEventBuildingFunctions_{
1489 :
1490 0 : [this] { return this->FormatEVBLocalParitionIDMACIndex(); },
1491 0 : [this] { return this->FormatEVBClusterInfo(); },
1492 0 : [this] { return this->FormatCFOTXClockMarkerCountLink6(); },
1493 0 : [this] { return this->FormatTXEventWindowMarkerCountLink(DTC_Link_CFO); },
1494 0 : [this] { return this->FormatTXHeartbeatPacketCountLink(DTC_Link_CFO); },
1495 0 : [this] { return this->FormatCFOLinkError(); },
1496 0 : [this] { return this->FormatEVBPacketControlInfo(); },
1497 0 : [this] { return this->FormatEVBStats(); },
1498 :
1499 : };
1500 : };
1501 : } // namespace DTCLib
1502 :
1503 : #endif // DTC_REGISTERS_H
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