Line data Source code
1 : #include "CFOandDTC_Registers.h"
2 :
3 : #include <assert.h>
4 : #include <unistd.h>
5 : #include <chrono>
6 : #include <cmath>
7 : #include <iomanip> // std::setw, std::setfill
8 : #include <sstream> // Convert uint to hex string
9 :
10 : #include "TRACE/tracemf.h"
11 :
12 : #include "dtcInterfaceLib/otsStyleCoutMacros.h"
13 :
14 : #undef __COUT_HDR__
15 : #define __COUT_HDR__ "core-CFOandDTC " << device_.getDeviceUID() << ": "
16 : #define TLVL_ResetDTC TLVL_DEBUG + 5
17 : #define TLVL_AutogenDRP TLVL_DEBUG + 6
18 : #define TLVL_SERDESReset TLVL_DEBUG + 7
19 : #define TLVL_CalculateFreq TLVL_DEBUG + 8
20 : #define TLVL_ReadRegister TLVL_DEBUG + 20
21 :
22 : using namespace DTCLib;
23 :
24 : // struct CFOandDTC_Register {
25 : enum CFOandDTC_Register : uint16_t
26 : {
27 : DTCLIB_COMMON_REGISTERS
28 : };
29 :
30 : // }; //end CFOandDTC_Register enum
31 :
32 : /// <summary>
33 : /// Construct an instance of the core CFO-and-DTC register map
34 : /// </summary>
35 0 : DTCLib::CFOandDTC_Registers::CFOandDTC_Registers()
36 0 : : device_()
37 : {
38 0 : } // end constructor()
39 :
40 : /// <summary>
41 : /// CFOandDTC_Registers destructor
42 : /// </summary>
43 0 : DTCLib::CFOandDTC_Registers::~CFOandDTC_Registers()
44 : {
45 0 : TLOG(TLVL_TRACE) << "DESTRUCTOR";
46 0 : } // end destructor()
47 :
48 : /// <summary>
49 : /// Perform a register dump
50 : /// </summary>
51 : /// <param name="width">Printable width of description fields</param>
52 : /// <returns>String containing all registers, with their human-readable representations</returns>
53 0 : std::string DTCLib::CFOandDTC_Registers::FormattedRegDump(int width,
54 : const std::vector<std::function<RegisterFormatter()>>& regVec)
55 : {
56 0 : formatterWidth_ = width - 27 - 65;
57 0 : if (formatterWidth_ < 28)
58 0 : formatterWidth_ = 28;
59 :
60 0 : std::string divider(formatterWidth_ + 27, '=');
61 :
62 0 : std::string spaces(formatterWidth_ - 4 - 9, ' ');
63 0 : std::ostringstream o;
64 0 : o << "Register Dump: " << std::endl;
65 0 : o << divider << std::endl;
66 : { // move address to right-align with values
67 0 : std::string placeholder = "";
68 0 : placeholder.resize(formatterWidth_ - 7, ' ');
69 0 : o << placeholder;
70 0 : }
71 0 : o << "Address | Hex Value |\nRegister Name " << spaces << "| (Translation)" << std::endl;
72 : { // move RegisterFormatter to right-align with values
73 0 : std::string placeholder = "";
74 0 : placeholder.resize(formatterWidth_, ' ');
75 0 : o << placeholder << " | Decorated Values" << std::endl;
76 0 : }
77 0 : for (auto i : regVec)
78 : {
79 0 : o << divider << std::endl;
80 0 : o << i();
81 0 : }
82 0 : return o.str();
83 0 : } // end FormattedRegDump()
84 :
85 : // Desgin Version/Date Registers
86 : /// <summary>
87 : /// Read the design version
88 : /// </summary>
89 : /// <returns>Design version, in VersionNumber_Date format</returns>
90 0 : std::string DTCLib::CFOandDTC_Registers::ReadDesignVersion() { return // ReadDesignVersionNumber() + "_" +
91 0 : ReadDesignDate() + ", Vivado Version: " + ReadVivadoVersionNumber() +
92 0 : ", Link Speed: " + ReadDesignLinkSpeed() + "_" + ReadDesignType(); }
93 :
94 : /// <summary>
95 : /// Formats the register's current value for register dumps
96 : /// </summary>
97 : /// <returns>RegisterFormatter object containing register information</returns>
98 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatDesignVersion()
99 : {
100 0 : auto form = CreateFormatter(CFOandDTC_Register_DesignVersion);
101 0 : form.description = "DTC Firmware Design Version";
102 0 : form.vals.push_back(std::string("Version Number: [") + ReadDesignVersionNumber(form.value) + "]");
103 0 : form.vals.push_back(std::string("Link Speed CFO link/ROC links: [") + ReadDesignLinkSpeed(form.value) + "]");
104 0 : form.vals.push_back(std::string("Design Type (C=CFO, D=DTC): [") + ReadDesignType(form.value) + "]");
105 0 : return form;
106 0 : }
107 :
108 : /// <summary>
109 : /// Read the modification date of the DTC firmware
110 : /// </summary>
111 : /// <returns>Design date in MON/DD/20YY HH:00 format</returns>
112 0 : std::string DTCLib::CFOandDTC_Registers::ReadDesignDate(std::optional<uint32_t> val)
113 : {
114 0 : auto readData = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignDate);
115 0 : std::ostringstream o;
116 0 : bool isCFO = false;
117 0 : std::vector<std::string> months({"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"});
118 0 : size_t mon = ((readData >> 20) & 0xF) * 10 + ((readData >> 16) & 0xF);
119 0 : if (mon - 1 >= months.size())
120 : {
121 0 : __SS__ << "Invalid register read for firmware design date month index: " + std::to_string(mon) << " in hex read-data 0x" << std::hex << readData << ". If the value is 0 or 165, this likely means the PCIe is not initialized and perhaps a PCIe reset of the Linux system would fix the issue.";
122 0 : __SS_THROW__;
123 0 : }
124 0 : if (((readData >> 28) & 0xF) == 0xA)
125 0 : o << "SIM-";
126 0 : else if (((readData >> 28) & 0xF) == 0xC)
127 : {
128 0 : o << "CFO-";
129 0 : isCFO = true;
130 : }
131 0 : else if (((readData >> 28) & 0xF) == 0xD)
132 0 : o << "DTC-";
133 0 : else if (((readData >> 28) & 0xF) == 0xE)
134 0 : o << "CRVDTC-";
135 0 : else if (((readData >> 28) & 0xF) == 0xF)
136 0 : o << "TEMP-";
137 0 : o << months[mon - 1] << "/" << ((readData >> 12) & 0xF) << ((readData >> 8) & 0xF) << "/20" <<
138 : // ((readData>>28)&0xF) <<
139 0 : (((readData >> 28) & 0xF) == 0x1 ? // if 1, then old!!! firmware
140 0 : (10 + ((readData >> 24) & 0xF))
141 0 : : (20 + ((readData >> 24) & 0xF)))
142 0 : << " " << // year 2020 + hex nibble at bit-24
143 0 : ((readData >> 4) & 0x7) << ((readData >> 0) & 0xF) << ":00 ";
144 0 : if (isCFO)
145 0 : o << "8-Links";
146 : else
147 0 : o << (((readData >> 7) & 0x1) ? "6-ROC" : "3-ROC");
148 0 : o << " raw-data: 0x" << std::hex << readData;
149 0 : return o.str();
150 0 : }
151 :
152 : /// <summary>
153 : /// Checks if is CRV DTC version
154 : /// </summary>
155 : /// <returns>returns true if the firmware is CRV DTC version, false otherwise</returns>
156 0 : bool DTCLib::CFOandDTC_Registers::isCRVDTCDesignFlavour(std::optional<uint32_t> val)
157 : {
158 0 : auto readData = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignDate);
159 0 : return ((readData >> 28) & 0xF) == 0xe;
160 : }
161 :
162 : /// <summary>
163 : /// Checks if is nonCRV DTC version
164 : /// </summary>
165 : /// <returns>returns true if the firmware is nonCRV DTC version, false otherwise</returns>
166 0 : bool DTCLib::CFOandDTC_Registers::isNonCRVDTCDesignFlavour(std::optional<uint32_t> val)
167 : {
168 0 : auto readData = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignDate);
169 0 : return ((readData >> 28) & 0xF) == 0xd;
170 : }
171 :
172 : /// <summary>
173 : /// Checks if is CFO version
174 : /// </summary>
175 : /// <returns>returns true if the firmware is CFO version, false otherwise</returns>
176 0 : bool DTCLib::CFOandDTC_Registers::isCFODesignFlavour(std::optional<uint32_t> val)
177 : {
178 0 : auto readData = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignDate);
179 0 : return ((readData >> 28) & 0xF) == 0xc;
180 : }
181 :
182 : /// <summary>
183 : /// Formats the register's current value for register dumps
184 : /// </summary>
185 : /// <returns>RegisterFormatter object containing register information</returns>
186 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatDesignDate()
187 : {
188 0 : auto form = CreateFormatter(CFOandDTC_Register_DesignDate);
189 0 : form.description = "DTC Firmware Design Date";
190 0 : form.vals.push_back(ReadDesignDate(form.value));
191 0 : return form;
192 0 : }
193 :
194 : /// <summary>
195 : /// Read the design version number
196 : /// </summary>
197 : /// <returns>The design version number, in vMM.mm format</returns>
198 0 : std::string DTCLib::CFOandDTC_Registers::ReadDesignVersionNumber(std::optional<uint32_t> val)
199 : {
200 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignVersion);
201 0 : int minor = data & 0xFF;
202 0 : int major = (data & 0xFF00) >> 8;
203 :
204 0 : __COUT_INFO__ << "Kernel Driver Version: " << GetDevice()->get_driver_version() << "Kernel Driver Version: " << GetDevice()->get_driver_version();
205 0 : return "v" + std::to_string(major) + "." + std::to_string(minor);
206 : } // end ReadDesignVersionNumber()
207 :
208 : /// <summary>
209 : /// Read the design link speed
210 : /// </summary>
211 : /// <returns>The design link speed, in hex character format</returns>
212 0 : std::string DTCLib::CFOandDTC_Registers::ReadDesignLinkSpeed(std::optional<uint32_t> val)
213 : {
214 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignVersion);
215 0 : int cfoLinkSpeed = (data >> 28) & 0xF; // bit28: 3, 4, or 5 Indicates Firmware configured for 3.125, 4.0, or 4.8 Gbps on CFO Link SERDES
216 0 : int rocLinkSpeed = (data >> 24) & 0xF; // bit24: 3, 4, or 5 Indicates Firmware configured for 3.125, 4.0, or 4.8 Gbps on ROC Link SERDES
217 :
218 0 : std::string cfoLinkSpeedStr = "?Gbps";
219 0 : if (cfoLinkSpeed == 3)
220 0 : cfoLinkSpeedStr = "3.125Gbps";
221 0 : else if (cfoLinkSpeed == 4)
222 0 : cfoLinkSpeedStr = "4.0Gbps";
223 0 : else if (cfoLinkSpeed == 5)
224 0 : cfoLinkSpeedStr = "4.8Gbps";
225 :
226 0 : std::string rocLinkSpeedStr = "?Gbps";
227 0 : if (rocLinkSpeed == 3)
228 0 : rocLinkSpeedStr = "3.125Gbps";
229 0 : else if (rocLinkSpeed == 4)
230 0 : rocLinkSpeedStr = "4.0Gbps";
231 0 : else if (rocLinkSpeed == 5)
232 0 : rocLinkSpeedStr = "4.8Gbps";
233 :
234 0 : return cfoLinkSpeedStr + "/" + rocLinkSpeedStr;
235 0 : } // end ReadDesignLinkSpeed()
236 :
237 : /// <summary>
238 : /// Read the design type
239 : /// </summary>
240 : /// <returns>The design link type, 0xC for CFO and 0xD for DTC </returns>
241 0 : std::string DTCLib::CFOandDTC_Registers::ReadDesignType(std::optional<uint32_t> val)
242 : {
243 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_DesignVersion);
244 0 : int type = (data >> 16) & 0xF; // 0xC for CFO and 0xD for DTC
245 0 : return (type == 0xC ? "C" : (type == 0xD ? "D" : "U")); // U for unknown!
246 : } // end ReadDesignLinkSpeed()
247 :
248 : /// <summary>
249 : /// Read the Vivado Version Number
250 : /// </summary>
251 : /// <returns>The Vivado Version number</returns>
252 0 : std::string DTCLib::CFOandDTC_Registers::ReadVivadoVersionNumber(std::optional<uint32_t> val)
253 : {
254 0 : auto data = val.has_value() ? (*val) : ReadRegister_(CFOandDTC_Register_VivadoVersion);
255 0 : std::ostringstream o;
256 0 : int yearHex = (data & 0xFFFF0000) >> 16;
257 0 : auto year = ((yearHex & 0xF000) >> 12) * 1000 + ((yearHex & 0xF00) >> 8) * 100 + ((yearHex & 0xF0) >> 4) * 10 +
258 0 : (yearHex & 0xF);
259 0 : int versionHex = (data & 0xFFFF);
260 0 : auto version = ((versionHex & 0xF000) >> 12) * 1000 + ((versionHex & 0xF00) >> 8) * 100 +
261 0 : ((versionHex & 0xF0) >> 4) * 10 + (versionHex & 0xF);
262 0 : o << std::setfill('0') << std::setw(4) << year << "-" << version;
263 : // std::cout << o.str() << std::endl;
264 0 : return o.str();
265 0 : }
266 :
267 : /// <summary>
268 : /// Formats the register's current value for register dumps
269 : /// </summary>
270 : /// <returns>RegisterFormatter object containing register information</returns>
271 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatVivadoVersion()
272 : {
273 0 : auto form = CreateFormatter(CFOandDTC_Register_VivadoVersion);
274 0 : form.description = "Firmware Project Vivado Version";
275 0 : form.vals.push_back(ReadVivadoVersionNumber(form.value));
276 0 : return form;
277 0 : }
278 :
279 : /// <summary>
280 : /// Perform a Soft Reset
281 : /// </summary>
282 0 : void DTCLib::CFOandDTC_Registers::SoftReset()
283 : {
284 0 : TLOG(TLVL_ResetDTC) << __COUT_HDR__ << "Soft Reset start";
285 0 : device_.resetSpyHasOccurred(); // allow spy() to fire again after a reset
286 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
287 0 : data[31] = 1; // set Soft Reset bit
288 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
289 : // NOTE: newer DTC versions (roughly > August 2023), self-clear the reset bit
290 : // NOTE: newer CFO versions (roughly > December 2023), do not self-clear the reset bit
291 0 : data = ReadRegister_(CFOandDTC_Register_Control); // re-read in case there are defaults applied at Soft Reset moment
292 0 : data[31] = 0; // clear Soft Reset bit
293 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
294 0 : }
295 :
296 : /// <summary>
297 : /// Read the Soft Reset control Bit
298 : /// </summary>
299 : /// <returns>True if the Soft Reset is currently resetting, false otherwise</returns>
300 0 : bool DTCLib::CFOandDTC_Registers::ReadSoftReset(std::optional<uint32_t> val)
301 : {
302 0 : std::bitset<32> dataSet = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_Control);
303 0 : return dataSet[31];
304 : }
305 :
306 : /// <summary>
307 : /// Set the SERDES Global Reset bit to true, and wait for the reset to complete
308 : /// </summary>
309 0 : void DTCLib::CFOandDTC_Registers::ResetSERDES()
310 : {
311 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
312 0 : data[8] = 1;
313 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
314 0 : usleep(1000);
315 : // does not self clear!
316 : // while (ReadResetSERDES())
317 : // {
318 : // usleep(1000);
319 : // }
320 0 : data[8] = 0;
321 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
322 0 : }
323 :
324 : /// <summary>
325 : /// Read the SERDES Global Reset bit
326 : /// </summary>
327 : /// <returns>Whether a SERDES global reset is in progress</returns>
328 0 : bool DTCLib::CFOandDTC_Registers::ReadResetSERDES(std::optional<uint32_t> val)
329 : {
330 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_Control);
331 0 : return data[8];
332 : }
333 :
334 : /// <summary>
335 : /// Read the Punched Clock Enable bit
336 : /// </summary>
337 : /// <returns>Whether punched clocks are enabled</returns>
338 0 : bool DTCLib::CFOandDTC_Registers::ReadPunchEnable(std::optional<uint32_t> val)
339 : {
340 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_Control);
341 0 : return data[9];
342 : }
343 :
344 0 : void DTCLib::CFOandDTC_Registers::SetPunchEnable()
345 : {
346 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
347 0 : data[9] = 1;
348 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
349 0 : }
350 :
351 0 : void DTCLib::CFOandDTC_Registers::ClearPunchEnable()
352 : {
353 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
354 0 : data[9] = 0;
355 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
356 0 : }
357 :
358 : /// <summary>
359 : /// Runs the Loopback test of the CFO Emulator, inside the DTC, and broadcasts loopback markers to all ROCs.
360 : /// </summary>
361 0 : void DTCLib::CFOandDTC_Registers::RunCableDelayLoopbackTest()
362 : {
363 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
364 0 : data[3] = 0;
365 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
366 0 : data[3] = 1;
367 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
368 0 : } // end RunCableDelayLoopbackTest()
369 :
370 : /// <summary>
371 : /// Perform a Hard Reset
372 : /// </summary>
373 0 : void DTCLib::CFOandDTC_Registers::HardReset()
374 : {
375 0 : TLOG(TLVL_ResetDTC) << __COUT_HDR__ << "Soft Reset start";
376 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_Control);
377 0 : data[0] = 1; // set Hard Reset bit
378 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
379 : // NOTE: only implemented in newer CFO and DTC versions (roughly > December 2023), and is implemented as a self-clear the reset bit
380 : // data = ReadRegister_(CFOandDTC_Register_Control); //re-read in case there are defaults applied at Soft Reset moment
381 : // data[0] = 0; // clear Hard Reset bit
382 : // WriteRegister_(data.to_ulong(), CFOandDTC_Register_Control);
383 0 : }
384 :
385 : /// <summary>
386 : /// Read the Hard Reset control Bit
387 : /// </summary>
388 : /// <returns>True if the Soft Reset is currently resetting, false otherwise</returns>
389 0 : bool DTCLib::CFOandDTC_Registers::ReadHardReset(std::optional<uint32_t> val)
390 : {
391 0 : std::bitset<32> dataSet = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_Control);
392 0 : return dataSet[0];
393 : }
394 :
395 : /// <summary>
396 : /// Clear the Control Register
397 : /// </summary>
398 0 : void DTCLib::CFOandDTC_Registers::ClearControlRegister()
399 : {
400 0 : WriteRegister_(0, CFOandDTC_Register_Control);
401 0 : }
402 :
403 : /// <summary>
404 : /// Read the FPGA On-die Temperature sensor
405 : /// </summary>
406 : /// <returns>Temperature of the FGPA (deg. C)</returns>
407 0 : double DTCLib::CFOandDTC_Registers::ReadFPGATemperature(std::optional<uint32_t> val)
408 : {
409 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_Temperature);
410 :
411 0 : return ((data * 503.975) / 4096.0) - 273.15;
412 : }
413 :
414 : /// <summary>
415 : /// Formats the register's current value for register dumps
416 : /// </summary>
417 : /// <returns>RegisterFormatter object containing register information</returns>
418 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFPGATemperature()
419 : {
420 0 : auto form = CreateFormatter(CFOandDTC_Register_FPGA_Temperature);
421 0 : form.description = "FPGA Temperature";
422 0 : form.vals.push_back(std::to_string(ReadFPGATemperature(form.value)) + " C");
423 0 : return form;
424 0 : }
425 :
426 : /// <summary>
427 : /// Read the FPGA VCC INT Voltage (Nominal is 1.0 V)
428 : /// </summary>
429 : /// <returns>FPGA VCC INT Voltage (V)</returns>
430 0 : double DTCLib::CFOandDTC_Registers::ReadFPGAVCCINTVoltage(std::optional<uint32_t> val)
431 : {
432 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_VCCINT);
433 0 : return (data / 4095.0) * 3.0;
434 : }
435 :
436 : /// <summary>
437 : /// Formats the register's current value for register dumps
438 : /// </summary>
439 : /// <returns>RegisterFormatter object containing register information</returns>
440 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFPGAVCCINT()
441 : {
442 0 : auto form = CreateFormatter(CFOandDTC_Register_FPGA_VCCINT);
443 0 : form.description = "FPGA VCC INT";
444 0 : form.vals.push_back(std::to_string(ReadFPGAVCCINTVoltage(form.value)) + " V");
445 0 : return form;
446 0 : }
447 :
448 : /// <summary>
449 : /// Read the FPGA VCC AUX Voltage (Nominal is 1.8 V)
450 : /// </summary>
451 : /// <returns>FPGA VCC AUX Voltage (V)</returns>
452 0 : double DTCLib::CFOandDTC_Registers::ReadFPGAVCCAUXVoltage(std::optional<uint32_t> val)
453 : {
454 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_VCCAUX);
455 0 : return (data / 4095.0) * 3.0;
456 : }
457 :
458 : /// <summary>
459 : /// Formats the register's current value for register dumps
460 : /// </summary>
461 : /// <returns>RegisterFormatter object containing register information</returns>
462 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFPGAVCCAUX()
463 : {
464 0 : auto form = CreateFormatter(CFOandDTC_Register_FPGA_VCCAUX);
465 0 : form.description = "FPGA VCC AUX";
466 0 : form.vals.push_back(std::to_string(ReadFPGAVCCAUXVoltage(form.value)) + " V");
467 0 : return form;
468 0 : }
469 :
470 : /// <summary>
471 : /// Read the FPGA VCC BRAM Voltage (Nominal 1.0 V)
472 : /// </summary>
473 : /// <returns>FPGA VCC BRAM Voltage (V)</returns>
474 0 : double DTCLib::CFOandDTC_Registers::ReadFPGAVCCBRAMVoltage(std::optional<uint32_t> val)
475 : {
476 0 : auto data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_VCCBRAM);
477 0 : return (data / 4095.0) * 3.0;
478 : }
479 :
480 : /// <summary>
481 : /// Formats the register's current value for register dumps
482 : /// </summary>
483 : /// <returns>RegisterFormatter object containing register information</returns>
484 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFPGAVCCBRAM()
485 : {
486 0 : auto form = CreateFormatter(CFOandDTC_Register_FPGA_VCCBRAM);
487 0 : form.description = "FPGA VCC BRAM";
488 0 : form.vals.push_back(std::to_string(ReadFPGAVCCBRAMVoltage(form.value)) + " V");
489 0 : return form;
490 0 : }
491 :
492 : /// <summary>
493 : /// Read the value of the FPGA Die Temperature Alarm bit
494 : /// </summary>
495 : /// <returns>Value of the bit</returns>
496 0 : bool DTCLib::CFOandDTC_Registers::ReadFPGADieTemperatureAlarm(std::optional<uint32_t> val)
497 : {
498 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
499 0 : return data[8];
500 : }
501 :
502 : /// <summary>
503 : /// Reset the FPGA Die Temperature Alarm bit
504 : /// </summary>
505 0 : void DTCLib::CFOandDTC_Registers::ResetFPGADieTemperatureAlarm(std::optional<uint32_t> val)
506 : {
507 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
508 0 : data[8] = 1;
509 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
510 0 : }
511 :
512 : /// <summary>
513 : /// Read the FPGA Alarms bit (OR of VCC and User Temperature alarm bits)
514 : /// </summary>
515 : /// <returns>Value of the bit</returns>
516 0 : bool DTCLib::CFOandDTC_Registers::ReadFPGAAlarms(std::optional<uint32_t> val)
517 : {
518 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
519 0 : return data[7];
520 : }
521 :
522 : /// <summary>
523 : /// Reset the FPGA Alarms bit
524 : /// </summary>
525 0 : void DTCLib::CFOandDTC_Registers::ResetFPGAAlarms(std::optional<uint32_t> val)
526 : {
527 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
528 0 : data[7] = 1;
529 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
530 0 : }
531 :
532 : /// <summary>
533 : /// Read the VCC BRAM Alarm bit
534 : /// </summary>
535 : /// <returns>Value of the bit</returns>
536 0 : bool DTCLib::CFOandDTC_Registers::ReadVCCBRAMAlarm(std::optional<uint32_t> val)
537 : {
538 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
539 0 : return data[3];
540 : }
541 :
542 : /// <summary>
543 : /// Reset the VCC BRAM Alarm bit
544 : /// </summary>
545 0 : void DTCLib::CFOandDTC_Registers::ResetVCCBRAMAlarm(std::optional<uint32_t> val)
546 : {
547 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
548 0 : data[3] = 1;
549 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
550 0 : }
551 :
552 : /// <summary>
553 : /// Read the VCC AUX Alarm bit
554 : /// </summary>
555 : /// <returns>Value of the bit</returns>
556 0 : bool DTCLib::CFOandDTC_Registers::ReadVCCAUXAlarm(std::optional<uint32_t> val)
557 : {
558 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
559 0 : return data[2];
560 : }
561 :
562 : /// <summary>
563 : /// Reset the VCC AUX Alarm bit
564 : /// </summary>
565 0 : void DTCLib::CFOandDTC_Registers::ResetVCCAUXAlarm(std::optional<uint32_t> val)
566 : {
567 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
568 0 : data[2] = 1;
569 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
570 0 : }
571 :
572 : /// <summary>
573 : /// Read the VCC INT Alarm bit
574 : /// </summary>
575 : /// <returns>Value of the bit</returns>
576 0 : bool DTCLib::CFOandDTC_Registers::ReadVCCINTAlarm(std::optional<uint32_t> val)
577 : {
578 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
579 0 : return data[1];
580 : }
581 :
582 : /// <summary>
583 : /// Reset the VCC INT Alarm bit
584 : /// </summary>
585 0 : void DTCLib::CFOandDTC_Registers::ResetVCCINTAlarm(std::optional<uint32_t> val)
586 : {
587 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
588 0 : data[1] = 1;
589 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
590 0 : }
591 :
592 : /// <summary>
593 : /// Read the FPGA User Temperature Alarm bit
594 : /// </summary>
595 : /// <returns>Value of the bit</returns>
596 0 : bool DTCLib::CFOandDTC_Registers::ReadFPGAUserTemperatureAlarm(std::optional<uint32_t> val)
597 : {
598 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
599 0 : return data[0];
600 : }
601 :
602 : /// <summary>
603 : /// Reset the FPGA User Temperature Alarm bit
604 : /// </summary>
605 0 : void DTCLib::CFOandDTC_Registers::ResetFPGAUserTemperatureAlarm(std::optional<uint32_t> val)
606 : {
607 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FPGA_MonitorAlarm);
608 0 : data[0] = 1;
609 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FPGA_MonitorAlarm);
610 0 : }
611 :
612 : /// <summary>
613 : /// Formats the register's current value for register dumps
614 : /// </summary>
615 : /// <returns>RegisterFormatter object containing register information</returns>
616 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFPGAAlarms()
617 : {
618 0 : auto form = CreateFormatter(CFOandDTC_Register_FPGA_MonitorAlarm);
619 0 : form.description = "FPGA Monitor Alarm";
620 0 : form.vals.push_back("[ x = 1 (hi) ]"); // translation
621 0 : form.vals.push_back(std::string("FPGA Die Temperature Alarm: [") + (ReadFPGADieTemperatureAlarm(form.value) ? "x" : " ") + "]");
622 0 : form.vals.push_back(std::string("FPGA Alarms OR: [") + (ReadFPGAAlarms(form.value) ? "x" : " ") + "]");
623 0 : form.vals.push_back(std::string("VCC BRAM Alarm: [") + (ReadVCCBRAMAlarm(form.value) ? "x" : " ") + "]");
624 0 : form.vals.push_back(std::string("VCC AUX Alarm: [") + (ReadVCCAUXAlarm(form.value) ? "x" : " ") + "]");
625 0 : form.vals.push_back(std::string("VCC INT Alarm: [") + (ReadVCCINTAlarm(form.value) ? "x" : " ") + "]");
626 0 : form.vals.push_back(std::string("FPGA User Temperature Alarm: [") + (ReadFPGAUserTemperatureAlarm(form.value) ? "x" : " ") + "]");
627 :
628 0 : return form;
629 0 : }
630 :
631 : /// <summary>
632 : /// Formats the device time alive register value as human-readable seconds
633 : /// </summary>
634 : /// <returns>RegisterFormatter object containing time alive information</returns>
635 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatDeviceTimeAlive()
636 : {
637 0 : auto form = CreateFormatter(CFOandDTC_Register_TimeAlive);
638 0 : form.description = "Device Time Alive";
639 0 : std::stringstream oss;
640 : // Resolution is 1/250MHz * 2^18 per LSB = 2^18 / 250e6 seconds per count
641 0 : double seconds = static_cast<double>(form.value) * (static_cast<double>(1 << 18) / 250e6);
642 0 : int totalSeconds = static_cast<int>(seconds);
643 0 : int days = totalSeconds / 86400;
644 0 : int hours = (totalSeconds / 3600) % 24;
645 0 : int minutes = (totalSeconds / 60) % 60;
646 0 : double secs = seconds - days * 86400 - hours * 3600 - minutes * 60;
647 0 : oss << std::setfill('0') << days << " days " << std::setw(2) << hours << ":"
648 0 : << std::setw(2) << minutes << ":" << std::setw(6) << std::fixed << std::setprecision(3)
649 0 : << secs << " (Firmware Version: " << ReadDesignDate() << ")";
650 0 : form.vals.push_back(oss.str());
651 0 : return form;
652 0 : }
653 :
654 : /// <summary>
655 : /// Formats the device hash of node + pcie index
656 : /// </summary>
657 : /// <returns>RegisterFormatter object containing hash information</returns>
658 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatDeviceHash()
659 : {
660 0 : auto form = CreateFormatter(CFOandDTC_Register_Scratch);
661 0 : form.description = "Device Hash";
662 0 : std::stringstream oss;
663 0 : oss << "Hash of Device Node and PCIe Index: 0x" << std::hex << mu2e_host_hash(device_.getDeviceIndex(), nullptr /* this host */) << std::dec;
664 0 : form.vals.push_back(oss.str());
665 0 : return form;
666 0 : }
667 :
668 : // Private Functions
669 0 : uint32_t DTCLib::CFOandDTC_Registers::WriteRegister_(uint32_t dataToWrite, const CFOandDTC_Register& address)
670 : {
671 0 : auto retry = 3;
672 : int errorCode;
673 0 : bool needToVerify = NeedToVerifyRegisterWrite_(address);
674 0 : uint32_t readbackValue = needToVerify ? -1 : dataToWrite;
675 : do
676 : {
677 0 : if (needToVerify)
678 0 : errorCode = device_.write_register_checked(address, 100, dataToWrite, &readbackValue);
679 : else
680 0 : errorCode = device_.write_register(address, 100, dataToWrite);
681 :
682 0 : --retry;
683 0 : } while (retry > 0 && errorCode != 0);
684 0 : if (errorCode != 0)
685 : {
686 0 : __SS__ << "Error writing register 0x" << std::hex << static_cast<uint32_t>(address) << " " << errorCode;
687 : // CFO_DTC_TLOG(TLVL_ERROR) << ss.str();
688 0 : __SS_THROW__;
689 : // throw DTC_IOErrorException(errorCode);
690 0 : }
691 :
692 0 : if (TTEST(1))
693 : { // trace seems to ignore the std::setfill, so using stringstream
694 0 : std::stringstream o;
695 0 : o << "write value 0x" << std::setw(8) << std::setfill('0') << std::setprecision(8) << std::hex << static_cast<uint32_t>(dataToWrite)
696 0 : << " to register 0x" << std::setw(4) << std::setfill('0') << std::setprecision(4) << std::hex << static_cast<uint32_t>(address) << " needToVerify=" << needToVerify << std::endl;
697 0 : if (needToVerify)
698 0 : o << " ... readback 0x" << std::setw(8) << std::setfill('0') << std::setprecision(8) << std::hex << static_cast<uint32_t>(readbackValue) << std::endl;
699 0 : __COUTT__ << o.str();
700 0 : }
701 :
702 : // verify register readback
703 0 : if (needToVerify)
704 : {
705 : // readbackValue = ReadRegister_(address); //already read above by write_register_checked!
706 0 : if (!CFOandDTCVerifyRegisterWrite_(address, readbackValue, dataToWrite)) // first check if it is a core register, i.e. CFOandDTC*
707 0 : VerifyRegisterWrite_(address, readbackValue, dataToWrite); // virtual function call
708 0 : return readbackValue;
709 : } // end verify register readback
710 :
711 0 : return readbackValue;
712 : } // end WriteRegister_()
713 :
714 : // return false if not a core register, i.e. CFOandDTC*
715 0 : bool DTCLib::CFOandDTC_Registers::CFOandDTCVerifyRegisterWrite_(const CFOandDTC_Register& address, uint32_t readbackValue, uint32_t dataToWrite)
716 : {
717 : // verify register readback
718 : if (1)
719 : {
720 0 : bool isCoreRegister = false;
721 :
722 0 : switch (address) // handle special register checks by masking of DONT-CARE bits, or else check full 32 bits
723 : {
724 : //---------- CFO and DTC registers
725 0 : case CFOandDTC_Register_SERDESClock_IICBusLow: // lowest 16-bits are the I2C read value. So ignore in write validation
726 : case CFOandDTC_Register_FireflyRX_IICBusConfigLow: // lowest 16-bits are the I2C read value. So ignore in write validation
727 0 : dataToWrite &= 0xffff0000;
728 0 : readbackValue &= 0xffff0000;
729 0 : isCoreRegister = true;
730 0 : break;
731 0 : case CFOandDTC_Register_SERDESClock_IICBusHigh: // this is an I2C register, it clears bit-0 when transaction finishes
732 : {
733 0 : int i = -1;
734 0 : while ((dataToWrite & 0x1) && (readbackValue & 0x1)) // wait for I2C to clear...
735 : {
736 0 : readbackValue = ReadRegister_(address);
737 0 : usleep(100);
738 0 : if ((++i % 10) == 9)
739 0 : __COUT__ << "I2C waited " << i + 1 << " times..." << std::endl;
740 : }
741 : }
742 0 : dataToWrite &= ~1;
743 0 : readbackValue &= ~1;
744 0 : isCoreRegister = true;
745 0 : break;
746 0 : case CFOandDTC_Register_FireFlyControlStatus: // only 10:8 and 2:0 defined in Firefly control reg
747 0 : dataToWrite &= (0x7 << 8) | (0x7 << 0);
748 0 : readbackValue &= (0x7 << 8) | (0x7 << 0);
749 0 : isCoreRegister = true;
750 0 : break;
751 : // case : // upper 16-bits are part of I2C operation. So ignore in write validation
752 : // dataToWrite &= 0x0000ffff;
753 : // readbackValue &= 0x0000ffff;
754 : // isCoreRegister = true;
755 : // break;
756 0 : case CFOandDTC_Register_Control: // bit 0 and 31 are reset bits, and self-clear (effectively, write only), also bit-25 self-resets (mig reset)
757 0 : if ((dataToWrite >> 0) & 1)
758 0 : return true; // ignore check if hard reset bit-0 high, because factory defaults are not maintained here
759 0 : dataToWrite &= 0x7dffffff;
760 0 : readbackValue &= 0x7dffffff;
761 0 : isCoreRegister = true;
762 0 : break;
763 :
764 0 : default:; // do direct comparison of each bit
765 : } // end readback verification address case handling
766 :
767 0 : if (isCoreRegister && readbackValue != dataToWrite)
768 : {
769 : try
770 : {
771 0 : __SS__ << "Write check mismatch - "
772 0 : << "write value 0x" << std::setw(8) << std::setfill('0') << std::setprecision(8) << std::hex << static_cast<uint32_t>(dataToWrite)
773 0 : << " to register 0x" << std::setw(4) << std::setfill('0') << std::setprecision(4) << std::hex << static_cast<uint32_t>(address) << "... read back 0x" << std::setw(8) << std::setfill('0') << std::setprecision(8) << std::hex << static_cast<uint32_t>(readbackValue) << std::endl
774 0 : << std::endl
775 0 : << "If you do not understand this error, try checking the firmware version: " << ReadDesignDate() << std::endl;
776 0 : __SS_ONLY_THROW__;
777 0 : }
778 0 : catch (const std::runtime_error& e)
779 : {
780 0 : std::stringstream ss;
781 0 : ss << e.what();
782 : ss << "\n\nThe stack trace is as follows:\n"
783 0 : << otsStyleStackTrace() << __E__;
784 0 : __SS_THROW__;
785 0 : }
786 : }
787 0 : return isCoreRegister;
788 : } // end verify register readback
789 : return false;
790 :
791 : } // end VerifyRegisterWrite_()
792 :
793 0 : uint32_t DTCLib::CFOandDTC_Registers::ReadRegister_(const CFOandDTC_Register& address)
794 : {
795 0 : auto retry = 3;
796 : int errorCode;
797 : uint32_t data;
798 : do
799 : {
800 0 : errorCode = device_.read_register(address, 100, &data);
801 0 : --retry;
802 0 : } while (retry > 0 && errorCode != 0);
803 0 : if (errorCode != 0)
804 : {
805 0 : __SS__ << "Error reading register 0x" << std::setw(4) << std::setfill('0') << std::setprecision(4) << std::hex << static_cast<uint32_t>(address) << " " << errorCode;
806 0 : __SS_THROW__;
807 : // throw DTC_IOErrorException(errorCode);
808 0 : }
809 :
810 0 : if (address == CFOandDTC_Register_Control && data == uint32_t(-1))
811 : {
812 0 : __SS__ << "Invalid register read for the Control Register: " << data << ". If the value is all 1s (4294967295), this likely means the FPGA-PCIe interface in not initialized and perhaps a PCIe reset of the linux system would fix the issue.";
813 0 : __SS_THROW__;
814 0 : }
815 :
816 0 : if (TTEST(1))
817 : { // trace seems to ignore the std::setfill, so using stringstream
818 0 : std::stringstream o;
819 0 : o << "read value 0x" << std::setw(8) << std::setfill('0') << std::setprecision(8) << std::hex << static_cast<uint32_t>(data)
820 0 : << " from register 0x" << std::setw(4) << std::setfill('0') << std::setprecision(4) << std::hex << static_cast<uint32_t>(address) << std::endl;
821 0 : __COUTT__ << o.str();
822 0 : }
823 :
824 0 : return data;
825 : } // end ReadRegister_()
826 :
827 : //========================================================================
828 0 : bool DTCLib::CFOandDTC_Registers::GetBit_(const CFOandDTC_Register& address, size_t bit)
829 : {
830 0 : if (bit > 31)
831 : {
832 0 : __SS__ << "Cannot read bit " << bit << ", as it is out of range";
833 0 : __SS_THROW__;
834 : // throw std::out_of_range("Cannot read bit " + std::to_string(bit) + ", as it is out of range");
835 0 : }
836 0 : return std::bitset<32>(ReadRegister_(address))[bit];
837 : }
838 :
839 : //========================================================================
840 0 : void DTCLib::CFOandDTC_Registers::SetBit_(const CFOandDTC_Register& address, size_t bit, bool value)
841 : {
842 0 : if (bit > 31)
843 : {
844 0 : __SS__ << "Cannot set bit " << bit << ", as it is out of range";
845 0 : __SS_THROW__;
846 : // throw std::out_of_range("Cannot set bit " + std::to_string(bit) + ", as it is out of range");
847 0 : }
848 0 : auto regVal = std::bitset<32>(ReadRegister_(address));
849 0 : regVal[bit] = value;
850 0 : WriteRegister_(regVal.to_ulong(), address);
851 0 : }
852 :
853 : //========================================================================
854 : // Jitter Attenuator CSR Register
855 : /// <summary>
856 : /// Read the value of the Jitter Attenuator Select
857 : /// </summary>
858 : /// <returns>Jitter Attenuator Select value</returns>
859 0 : std::bitset<2> DTCLib::CFOandDTC_Registers::ReadJitterAttenuatorSelect(CFOandDTC_Register JAreg, std::optional<uint32_t> val)
860 : {
861 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(JAreg);
862 0 : std::bitset<2> output;
863 0 : output[0] = data[4];
864 0 : output[1] = data[5];
865 0 : return output;
866 : }
867 :
868 : //========================================================================
869 : /// <summary>
870 : /// Set the Jitter Attenuator Select bits. JA reset only needed after a power cycle
871 : /// </summary>
872 : /// <param name="data">Value to set</param>
873 0 : void DTCLib::CFOandDTC_Registers::SetJitterAttenuatorSelect(CFOandDTC_Register JAreg, std::bitset<2> data, bool alsoResetJA /* = false */)
874 : {
875 0 : __COUT__ << "JA select " << data << " = " << (data == 0 ? "CFO control link" : (data == 1 ? "RTF copper clock" : (data == 2 ? "FPGA FMC" : "undefined source!")));
876 : ;
877 0 : std::bitset<32> regdata = ReadRegister_(JAreg);
878 :
879 : // attempt detection if already locked with same input mux select, early exit
880 : // form.vals.push_back(std::string("JA in Reset: [") + (data[0] ? "YES" : "No") + "]");
881 : // form.vals.push_back(std::string("JA Loss-of-Lock: [") + (data[8] ? "Not Locked" : "LOCKED") + "]");
882 : // form.vals.push_back(std::string("JA Input-0 Upstream Control Link Rx Recovered Clock: [") + (data[9] ? "Missing" : "OK") + "]");
883 : // form.vals.push_back(std::string("JA Input-1 RJ45 Upstream Rx Clock: [") + (data[10] ? "Missing" : "OK") + "]");
884 : // form.vals.push_back(std::string("JA Input-2 Timing Card Selectable, SFP+ or FPGA, Input Clock: [") + (data[11] ? "Missing" : "OK") + "]");
885 0 : if (regdata[0] == 0 && regdata[8] == 0 && regdata[4] == data[0] && regdata[5] == data[1])
886 : {
887 0 : __COUT__ << "JA already locked with selected input " << data;
888 0 : return;
889 : }
890 0 : regdata[4] = data[0];
891 0 : regdata[5] = data[1];
892 0 : regdata = WriteRegister_(regdata.to_ulong(), JAreg);
893 :
894 0 : if (!alsoResetJA || regdata[8] == 0) // if locked, then do not reconfigure JA (JA only needs a reset after a cold start, usually indicated by lock)
895 : {
896 0 : __COUT__ << "JA select done with no reset for input " << data;
897 0 : return;
898 : }
899 :
900 0 : __COUT__ << "JA reset...";
901 :
902 0 : ResetJitterAttenuator(JAreg, regdata.to_ulong());
903 0 : sleep(1);
904 :
905 0 : ConfigureJitterAttenuator();
906 0 : __COUT__ << "JA select done for input " << data;
907 : } // end SetJitterAttenuatorSelect()
908 :
909 : //========================================================================
910 : /// <summary>
911 : /// Read the Jitter Attenuator Reset bit
912 : /// </summary>
913 : /// <returns>Value of the Jitter Attenuator Reset bit</returns>
914 0 : bool DTCLib::CFOandDTC_Registers::ReadJitterAttenuatorReset(CFOandDTC_Register JAreg, std::optional<uint32_t> val)
915 : {
916 0 : std::bitset<32> regdata = val.has_value() ? *val : ReadRegister_(JAreg);
917 0 : return regdata[0];
918 : } // end ReadJitterAttenuatorReset()
919 :
920 : //========================================================================
921 : /// <summary>
922 : /// Read the Jitter Attenuator Locked bit
923 : /// </summary>
924 : /// <returns>Inverted Value of the Jitter Attenuator Loss-of-Lock bit</returns>
925 0 : bool DTCLib::CFOandDTC_Registers::ReadJitterAttenuatorLocked(CFOandDTC_Register JAreg, std::optional<uint32_t> val)
926 : {
927 0 : std::bitset<32> regdata = val.has_value() ? *val : ReadRegister_(JAreg);
928 0 : return !regdata[8];
929 : } // end ReadJitterAttenuatorLocked()
930 :
931 : //========================================================================
932 : /// <summary>
933 : /// Reset the Jitter Attenuator
934 : /// </summary>
935 0 : void DTCLib::CFOandDTC_Registers::ResetJitterAttenuator(CFOandDTC_Register JAreg, std::optional<uint32_t> val)
936 : {
937 0 : std::bitset<32> regdata = val.has_value() ? *val : ReadRegister_(JAreg);
938 0 : regdata[0] = 1;
939 0 : WriteRegister_(regdata.to_ulong(), JAreg);
940 0 : usleep(1000);
941 0 : regdata[0] = 0;
942 0 : WriteRegister_(regdata.to_ulong(), JAreg);
943 0 : } // end ResetJitterAttenuator()
944 :
945 : //========================================================================
946 : /// <summary>
947 : /// Formats the register's current value for register dumps
948 : /// </summary>
949 : /// <returns>RegisterFormatter object containing register information</returns>
950 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatJitterAttenuatorCSR(CFOandDTC_Register JAreg)
951 : {
952 0 : auto form = CreateFormatter(JAreg);
953 0 : std::bitset<32> data = form.value;
954 0 : std::bitset<2> JAinputSelect;
955 0 : JAinputSelect[0] = data[4];
956 0 : JAinputSelect[1] = data[5];
957 0 : form.description = "Jitter Attenuator CSR";
958 0 : form.vals.push_back("<field> : [<value>]"); // first value describes format
959 0 : form.vals.push_back(std::string("JA Source Clock Select: [") +
960 0 : (JAinputSelect.to_ulong() == 0 ? "from internal CFO"
961 0 : : (JAinputSelect.to_ulong() == 1 ? "from RJ45"
962 0 : : "Timing Card Selectable (SFP+ or FPGA) Input Clock")) +
963 : "]");
964 0 : form.vals.push_back(std::string("JA in Reset: [") + (data[0] ? "YES" : "No") + "]");
965 0 : form.vals.push_back(std::string("JA Loss-of-Lock: [") + (data[8] ? "Not Locked" : "LOCKED") + "]");
966 0 : form.vals.push_back(std::string("JA Input-0 CFO (or emulated CFO) Clock Source: [") + (data[9] ? "Missing" : "OK") + "]");
967 0 : form.vals.push_back(std::string("JA Input-1 RJ45 Clock Source: [") + (data[10] ? "Missing" : "OK") + "]");
968 0 : form.vals.push_back(std::string("JA Input-2 Timing Card Selectable, SFP+ or FPGA, Input Clock: [") + (data[11] ? "Missing" : "OK") + "]");
969 0 : return form;
970 0 : } // end FormatJitterAttenuatorCSR()
971 :
972 : /// <summary>
973 : /// Write a value to the SERDES IIC Bus
974 : /// </summary>
975 : /// <param name="device">Device address</param>
976 : /// <param name="address">Register address</param>
977 : /// <param name="data">Data to write</param>
978 0 : void DTCLib::CFOandDTC_Registers::WriteSERDESIICInterface(DTC_IICSERDESBusAddress device, uint8_t address, uint8_t data)
979 : {
980 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16) + (data << 8);
981 0 : WriteRegister_(reg_data, CFOandDTC_Register_SERDESClock_IICBusLow);
982 0 : WriteRegister_(0x1, CFOandDTC_Register_SERDESClock_IICBusHigh);
983 0 : u_int16_t retries = 1000;
984 0 : while (ReadRegister_(CFOandDTC_Register_SERDESClock_IICBusHigh) == 0x1)
985 : {
986 0 : if (--retries == 0)
987 : {
988 0 : __SS__ << "Timeout waiting for I2C interface to write!" << __E__;
989 0 : __SS_THROW__;
990 0 : }
991 0 : usleep(1000);
992 : }
993 0 : }
994 :
995 : /// <summary>
996 : /// Read a value from the SERDES IIC Bus
997 : /// </summary>
998 : /// <param name="device">Device address</param>
999 : /// <param name="address">Register address</param>
1000 : /// <returns>Value of register</returns>
1001 0 : uint8_t DTCLib::CFOandDTC_Registers::ReadSERDESIICInterface(DTC_IICSERDESBusAddress device, uint8_t address)
1002 : {
1003 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16);
1004 0 : WriteRegister_(reg_data, CFOandDTC_Register_SERDESClock_IICBusLow);
1005 0 : WriteRegister_(0x2, CFOandDTC_Register_SERDESClock_IICBusHigh);
1006 0 : u_int16_t retries = 1000;
1007 0 : while (ReadRegister_(CFOandDTC_Register_SERDESClock_IICBusHigh) == 0x2)
1008 : {
1009 0 : if (--retries == 0)
1010 : {
1011 0 : __SS__ << "Timeout waiting for I2C interface to read!" << __E__;
1012 0 : __SS_THROW__;
1013 0 : }
1014 0 : usleep(1000);
1015 : }
1016 0 : auto data = ReadRegister_(CFOandDTC_Register_SERDESClock_IICBusLow);
1017 0 : return static_cast<uint8_t>(data);
1018 : }
1019 :
1020 : /// <summary>
1021 : /// Formats the register's current value for register dumps
1022 : /// </summary>
1023 : /// <returns>RegisterFormatter object containing register information</returns>
1024 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatSERDESOscillatorParameterLow()
1025 : {
1026 0 : auto form = CreateFormatter(CFOandDTC_Register_SERDESClock_IICBusLow);
1027 0 : form.description = "SERDES Oscillator IIC Bus Low";
1028 0 : form.vals.push_back(""); // translation
1029 0 : auto data = form.value;
1030 0 : std::ostringstream s1, s2, s3, s4;
1031 0 : s1 << "Device: " << std::showbase << std::hex << ((data & 0xFF000000) >> 24);
1032 0 : form.vals.push_back(s1.str());
1033 0 : s2 << "Address: " << std::showbase << std::hex << ((data & 0xFF0000) >> 16);
1034 0 : form.vals.push_back(s2.str());
1035 0 : s3 << "Write Data: " << std::showbase << std::hex << ((data & 0xFF00) >> 8);
1036 0 : form.vals.push_back(s3.str());
1037 0 : s4 << "Read Data: " << std::showbase << std::hex << (data & 0xFF);
1038 0 : form.vals.push_back(s4.str());
1039 0 : return form;
1040 0 : }
1041 :
1042 : /// <summary>
1043 : /// Formats the register's current value for register dumps
1044 : /// </summary>
1045 : /// <returns>RegisterFormatter object containing register information</returns>
1046 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatSERDESOscillatorParameterHigh()
1047 : {
1048 0 : auto form = CreateFormatter(CFOandDTC_Register_SERDESClock_IICBusHigh);
1049 0 : auto data = form.value;
1050 0 : form.description = "SERDES Oscillator IIC Bus High";
1051 0 : form.vals.push_back("([ x = 1 (hi) ])"); // translation
1052 0 : form.vals.push_back(std::string("Write: [") + (data & 0x1 ? "x" : " ") + "]");
1053 0 : form.vals.push_back(std::string("Read: [") + (data & 0x2 ? "x" : " ") + "]");
1054 0 : return form;
1055 0 : }
1056 :
1057 : // Firefly TX IIC Registers
1058 : /// <summary>
1059 : /// Read the Reset bit of the Firefly TX IIC Bus
1060 : /// </summary>
1061 : /// <returns>Reset bit value</returns>
1062 0 : bool DTCLib::CFOandDTC_Registers::ReadFireflyTXIICInterfaceReset(std::optional<uint32_t> val)
1063 : {
1064 0 : auto dataSet = std::bitset<32>(val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireflyTX_IICBusControl));
1065 0 : return dataSet[31];
1066 : }
1067 : /// <summary>
1068 : /// Reset the Firefly TX IIC Bus
1069 : /// </summary>
1070 0 : void DTCLib::CFOandDTC_Registers::ResetFireflyTXIICInterface()
1071 : {
1072 0 : auto bs = std::bitset<32>();
1073 0 : bs[31] = 1;
1074 0 : WriteRegister_(bs.to_ulong(), CFOandDTC_Register_FireflyTX_IICBusControl);
1075 0 : u_int16_t retries = 1000;
1076 0 : while (ReadFireflyTXIICInterfaceReset())
1077 : {
1078 0 : if (--retries == 0)
1079 : {
1080 0 : __SS__ << "Timeout waiting for I2C interface to reset!" << __E__;
1081 0 : __SS_THROW__;
1082 0 : }
1083 0 : usleep(1000);
1084 : }
1085 0 : }
1086 : /// <summary>
1087 : /// Write a value to the Firefly TX IIC Bus
1088 : /// </summary>
1089 : /// <param name="device">Device address</param>
1090 : /// <param name="address">Register address</param>
1091 : /// <param name="data">Data to write</param>
1092 0 : void DTCLib::CFOandDTC_Registers::WriteFireflyTXIICInterface(uint8_t device, uint8_t address, uint8_t data)
1093 : {
1094 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16) + (data << 8);
1095 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyTX_IICBusConfigLow);
1096 0 : WriteRegister_(0x1, CFOandDTC_Register_FireflyTX_IICBusConfigHigh);
1097 0 : u_int16_t retries = 1000;
1098 0 : while (ReadRegister_(CFOandDTC_Register_FireflyTX_IICBusConfigHigh) == 0x1)
1099 : {
1100 0 : if (--retries == 0)
1101 : {
1102 0 : __SS__ << "Timeout waiting for I2C interface to write!" << __E__;
1103 0 : __SS_THROW__;
1104 0 : }
1105 0 : usleep(1000);
1106 : }
1107 0 : }
1108 : /// <summary>
1109 : /// Read a value from the Firefly TX IIC Bus
1110 : /// </summary>
1111 : /// <param name="device">Device address</param>
1112 : /// <param name="address">Register address</param>
1113 : /// <returns>Value of register</returns>
1114 0 : uint8_t DTCLib::CFOandDTC_Registers::ReadFireflyTXIICInterface(uint8_t device, uint8_t address)
1115 : {
1116 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16);
1117 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyTX_IICBusConfigLow);
1118 0 : WriteRegister_(0x2, CFOandDTC_Register_FireflyTX_IICBusConfigHigh);
1119 0 : u_int16_t retries = 1000;
1120 0 : while (ReadRegister_(CFOandDTC_Register_FireflyTX_IICBusConfigHigh) == 0x2)
1121 : {
1122 0 : if (--retries == 0)
1123 : {
1124 0 : __SS__ << "Timeout waiting for I2C interface to read!" << __E__;
1125 0 : __SS_THROW__;
1126 0 : }
1127 0 : usleep(1000);
1128 : }
1129 0 : auto data = ReadRegister_(CFOandDTC_Register_FireflyTX_IICBusConfigLow);
1130 0 : return static_cast<uint8_t>(data);
1131 : }
1132 : /// <summary>
1133 : /// Formats the register's current value for register dumps
1134 : /// </summary>
1135 : /// <returns>RegisterFormatter object containing register information</returns>
1136 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXIICControl()
1137 : {
1138 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTX_IICBusControl);
1139 0 : form.description = "TX Firefly IIC Bus Control";
1140 0 : form.vals.push_back(std::string("Reset: [") + (ReadFireflyTXIICInterfaceReset(form.value) ? "x" : " ") + "]");
1141 0 : return form;
1142 0 : }
1143 : /// <summary>
1144 : /// Formats the register's current value for register dumps
1145 : /// </summary>
1146 : /// <returns>RegisterFormatter object containing register information</returns>
1147 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXIICParameterLow()
1148 : {
1149 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTX_IICBusConfigLow);
1150 0 : form.description = "TX Firefly IIC Bus Low";
1151 0 : form.vals.push_back(""); // translation
1152 0 : auto data = form.value;
1153 0 : std::ostringstream s1, s2, s3, s4;
1154 0 : s1 << "Device: " << std::showbase << std::hex << ((data & 0xFF000000) >> 24);
1155 0 : form.vals.push_back(s1.str());
1156 0 : s2 << "Address: " << std::showbase << std::hex << ((data & 0xFF0000) >> 16);
1157 0 : form.vals.push_back(s2.str());
1158 0 : s3 << "Write Data: " << std::showbase << std::hex << ((data & 0xFF00) >> 8);
1159 0 : form.vals.push_back(s3.str());
1160 0 : s4 << "Read Data: " << std::showbase << std::hex << (data & 0xFF);
1161 0 : form.vals.push_back(s4.str());
1162 0 : return form;
1163 0 : }
1164 : /// <summary>
1165 : /// Formats the register's current value for register dumps
1166 : /// </summary>
1167 : /// <returns>RegisterFormatter object containing register information</returns>
1168 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXIICParameterHigh()
1169 : {
1170 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTX_IICBusConfigHigh);
1171 0 : auto data = form.value;
1172 0 : form.description = "TX Firefly IIC Bus High";
1173 0 : form.vals.push_back("([ x = 1 (hi) ])"); // translation
1174 0 : form.vals.push_back(std::string("Write: [") + (data & 0x1 ? "x" : " ") + "]");
1175 0 : form.vals.push_back(std::string("Read: [") + (data & 0x2 ? "x" : " ") + "]");
1176 0 : return form;
1177 0 : }
1178 :
1179 : // Firefly RX IIC Registers
1180 : /// <summary>
1181 : /// Read the Reset bit of the Firefly RX IIC Bus
1182 : /// </summary>
1183 : /// <returns>Reset bit value</returns>
1184 0 : bool DTCLib::CFOandDTC_Registers::ReadFireflyRXIICInterfaceReset(std::optional<uint32_t> val)
1185 : {
1186 0 : auto dataSet = std::bitset<32>(val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireflyRX_IICBusControl));
1187 0 : return dataSet[31];
1188 : }
1189 : /// <summary>
1190 : /// Reset the Firefly RX IIC Bus
1191 : /// </summary>
1192 0 : void DTCLib::CFOandDTC_Registers::ResetFireflyRXIICInterface()
1193 : {
1194 0 : auto bs = std::bitset<32>();
1195 0 : bs[31] = 1;
1196 0 : WriteRegister_(bs.to_ulong(), CFOandDTC_Register_FireflyRX_IICBusControl);
1197 0 : u_int16_t retries = 1000;
1198 0 : while (ReadFireflyRXIICInterfaceReset())
1199 : {
1200 0 : if (--retries == 0)
1201 : {
1202 0 : __SS__ << "Timeout waiting for I2C interface to reset!" << __E__;
1203 0 : __SS_THROW__;
1204 0 : }
1205 0 : usleep(1000);
1206 : }
1207 0 : }
1208 : /// <summary>
1209 : /// Write a value to the Firefly RX IIC Bus
1210 : /// </summary>
1211 : /// <param name="device">Device address</param>
1212 : /// <param name="address">Register address</param>
1213 : /// <param name="data">Data to write</param>
1214 0 : void DTCLib::CFOandDTC_Registers::WriteFireflyRXIICInterface(uint8_t device, uint8_t address, uint8_t data)
1215 : {
1216 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16) + (data << 8);
1217 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyRX_IICBusConfigLow);
1218 0 : WriteRegister_(0x1, CFOandDTC_Register_FireflyRX_IICBusConfigHigh);
1219 0 : u_int16_t retries = 1000;
1220 0 : while (ReadRegister_(CFOandDTC_Register_FireflyRX_IICBusConfigHigh) == 0x1)
1221 : {
1222 0 : if (--retries == 0)
1223 : {
1224 0 : __SS__ << "Timeout waiting for I2C interface to write!" << __E__;
1225 0 : __SS_THROW__;
1226 0 : }
1227 0 : usleep(1000);
1228 : }
1229 0 : }
1230 : /// <summary>
1231 : /// Read a value from the Firefly RX IIC Bus
1232 : /// </summary>
1233 : /// <param name="device">Device address</param>
1234 : /// <param name="address">Register address</param>
1235 : /// <returns>Value of register</returns>
1236 0 : uint8_t DTCLib::CFOandDTC_Registers::ReadFireflyRXIICInterface(uint8_t device, uint8_t address)
1237 : {
1238 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16);
1239 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyRX_IICBusConfigLow);
1240 0 : WriteRegister_(0x2, CFOandDTC_Register_FireflyRX_IICBusConfigHigh);
1241 0 : u_int16_t retries = 1000;
1242 0 : while (ReadRegister_(CFOandDTC_Register_FireflyRX_IICBusConfigHigh) == 0x2)
1243 : {
1244 0 : if (--retries == 0)
1245 : {
1246 0 : __SS__ << "Timeout waiting for I2C interface to read!" << __E__;
1247 0 : __SS_THROW__;
1248 0 : }
1249 0 : usleep(1000);
1250 : }
1251 0 : auto data = ReadRegister_(CFOandDTC_Register_FireflyRX_IICBusConfigLow);
1252 0 : return static_cast<uint8_t>(data);
1253 : }
1254 : /// <summary>
1255 : /// Formats the register's current value for register dumps
1256 : /// </summary>
1257 : /// <returns>RegisterFormatter object containing register information</returns>
1258 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyRXIICControl()
1259 : {
1260 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyRX_IICBusControl);
1261 0 : form.description = "RX Firefly IIC Bus Control";
1262 0 : form.vals.push_back(std::string("Reset: [") + (ReadFireflyRXIICInterfaceReset(form.value) ? "x" : " ") + "]");
1263 0 : return form;
1264 0 : }
1265 : /// <summary>
1266 : /// Formats the register's current value for register dumps
1267 : /// </summary>
1268 : /// <returns>RegisterFormatter object containing register information</returns>
1269 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyRXIICParameterLow()
1270 : {
1271 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyRX_IICBusConfigLow);
1272 0 : form.description = "RX Firefly IIC Bus Low";
1273 0 : form.vals.push_back(""); // translation
1274 0 : auto data = form.value;
1275 0 : std::ostringstream s1, s2, s3, s4;
1276 0 : s1 << "Device: " << std::showbase << std::hex << ((data & 0xFF000000) >> 24);
1277 0 : form.vals.push_back(s1.str());
1278 0 : s2 << "Address: " << std::showbase << std::hex << ((data & 0xFF0000) >> 16);
1279 0 : form.vals.push_back(s2.str());
1280 0 : s3 << "Write Data: " << std::showbase << std::hex << ((data & 0xFF00) >> 8);
1281 0 : form.vals.push_back(s3.str());
1282 0 : s4 << "Read Data: " << std::showbase << std::hex << (data & 0xFF);
1283 0 : form.vals.push_back(s4.str());
1284 0 : return form;
1285 0 : }
1286 : /// <summary>
1287 : /// Formats the register's current value for register dumps
1288 : /// </summary>
1289 : /// <returns>RegisterFormatter object containing register information</returns>
1290 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyRXIICParameterHigh()
1291 : {
1292 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyRX_IICBusConfigHigh);
1293 0 : auto data = form.value;
1294 0 : form.description = "RX Firefly IIC Bus High";
1295 0 : form.vals.push_back("([ x = 1 (hi) ])"); // translation
1296 0 : form.vals.push_back(std::string("Write: [") + (data & 0x1 ? "x" : " ") + "]");
1297 0 : form.vals.push_back(std::string("Read: [") + (data & 0x2 ? "x" : " ") + "]");
1298 0 : return form;
1299 0 : }
1300 :
1301 : // Firefly TXRX IIC Registers
1302 : /// <summary>
1303 : /// Read the Reset bit of the Firefly TXRX IIC Bus
1304 : /// </summary>
1305 : /// <returns>Reset bit value</returns>
1306 0 : bool DTCLib::CFOandDTC_Registers::ReadFireflyTXRXIICInterfaceReset(std::optional<uint32_t> val)
1307 : {
1308 0 : auto dataSet = std::bitset<32>(val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireflyTXRX_IICBusControl));
1309 0 : return dataSet[31];
1310 : }
1311 : /// <summary>
1312 : /// Reset the Firefly TXRX IIC Bus
1313 : /// </summary>
1314 0 : void DTCLib::CFOandDTC_Registers::ResetFireflyTXRXIICInterface()
1315 : {
1316 0 : auto bs = std::bitset<32>();
1317 0 : bs[31] = 1;
1318 0 : WriteRegister_(bs.to_ulong(), CFOandDTC_Register_FireflyTXRX_IICBusControl);
1319 0 : u_int16_t retries = 1000;
1320 0 : while (ReadFireflyTXRXIICInterfaceReset())
1321 : {
1322 0 : if (--retries == 0)
1323 : {
1324 0 : __SS__ << "Timeout waiting for I2C interface to reset!" << __E__;
1325 0 : __SS_THROW__;
1326 0 : }
1327 0 : usleep(1000);
1328 : }
1329 0 : }
1330 : /// <summary>
1331 : /// Write a value to the Firefly TXRX IIC Bus
1332 : /// </summary>
1333 : /// <param name="device">Device address</param>
1334 : /// <param name="address">Register address</param>
1335 : /// <param name="data">Data to write</param>
1336 0 : void DTCLib::CFOandDTC_Registers::WriteFireflyTXRXIICInterface(uint8_t device, uint8_t address, uint8_t data)
1337 : {
1338 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16) + (data << 8);
1339 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyTXRX_IICBusConfigLow);
1340 0 : WriteRegister_(0x1, CFOandDTC_Register_FireflyTXRX_IICBusConfigHigh);
1341 0 : u_int16_t retries = 1000;
1342 0 : while (ReadRegister_(CFOandDTC_Register_FireflyTXRX_IICBusConfigHigh) == 0x1)
1343 : {
1344 0 : if (--retries == 0)
1345 : {
1346 0 : __SS__ << "Timeout waiting for I2C interface to write!" << __E__;
1347 0 : __SS_THROW__;
1348 0 : }
1349 0 : usleep(1000);
1350 : }
1351 0 : }
1352 : /// <summary>
1353 : /// Read a value from the Firefly TXRX IIC Bus
1354 : /// </summary>
1355 : /// <param name="device">Device address</param>
1356 : /// <param name="address">Register address</param>
1357 : /// <returns>Value of register</returns>
1358 0 : uint8_t DTCLib::CFOandDTC_Registers::ReadFireflyTXRXIICInterface(uint8_t device, uint8_t address)
1359 : {
1360 0 : uint32_t reg_data = (static_cast<uint8_t>(device) << 24) + (address << 16);
1361 0 : WriteRegister_(reg_data, CFOandDTC_Register_FireflyTXRX_IICBusConfigLow);
1362 0 : WriteRegister_(0x2, CFOandDTC_Register_FireflyTXRX_IICBusConfigHigh);
1363 0 : u_int16_t retries = 1000;
1364 0 : while (ReadRegister_(CFOandDTC_Register_FireflyTXRX_IICBusConfigHigh) == 0x2)
1365 : {
1366 0 : if (--retries == 0)
1367 : {
1368 0 : __SS__ << "Timeout waiting for I2C interface to read!" << __E__;
1369 0 : __SS_THROW__;
1370 0 : }
1371 0 : usleep(1000);
1372 : }
1373 0 : auto data = ReadRegister_(CFOandDTC_Register_FireflyTXRX_IICBusConfigLow);
1374 0 : return static_cast<uint8_t>(data);
1375 : }
1376 : /// <summary>
1377 : /// Formats the register's current value for register dumps
1378 : /// </summary>
1379 : /// <returns>RegisterFormatter object containing register information</returns>
1380 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXRXIICControl()
1381 : {
1382 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTXRX_IICBusControl);
1383 0 : form.description = "TXRX Firefly IIC Bus Control";
1384 0 : form.vals.push_back(std::string("Reset: [") + (ReadFireflyTXRXIICInterfaceReset(form.value) ? "x" : " ") + "]");
1385 0 : return form;
1386 0 : }
1387 : /// <summary>
1388 : /// Formats the register's current value for register dumps
1389 : /// </summary>
1390 : /// <returns>RegisterFormatter object containing register information</returns>
1391 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXRXIICParameterLow()
1392 : {
1393 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTXRX_IICBusConfigLow);
1394 0 : form.description = "TXRX Firefly IIC Bus Low";
1395 0 : form.vals.push_back(""); // translation
1396 0 : auto data = form.value;
1397 0 : std::ostringstream s1, s2, s3, s4;
1398 0 : s1 << "Device: " << std::showbase << std::hex << ((data & 0xFF000000) >> 24);
1399 0 : form.vals.push_back(s1.str());
1400 0 : s2 << "Address: " << std::showbase << std::hex << ((data & 0xFF0000) >> 16);
1401 0 : form.vals.push_back(s2.str());
1402 0 : s3 << "Write Data: " << std::showbase << std::hex << ((data & 0xFF00) >> 8);
1403 0 : form.vals.push_back(s3.str());
1404 0 : s4 << "Read Data: " << std::showbase << std::hex << (data & 0xFF);
1405 0 : form.vals.push_back(s4.str());
1406 0 : return form;
1407 0 : }
1408 : /// <summary>
1409 : /// Formats the register's current value for register dumps
1410 : /// </summary>
1411 : /// <returns>RegisterFormatter object containing register information</returns>
1412 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyTXRXIICParameterHigh()
1413 : {
1414 0 : auto form = CreateFormatter(CFOandDTC_Register_FireflyTXRX_IICBusConfigHigh);
1415 0 : auto data = form.value;
1416 0 : form.description = "TXRX Firefly IIC Bus High";
1417 0 : form.vals.push_back("([ x = 1 (hi) ])"); // translation
1418 0 : form.vals.push_back(std::string("Write: [") + (data & 0x1 ? "x" : " ") + "]");
1419 0 : form.vals.push_back(std::string("Read: [") + (data & 0x2 ? "x" : " ") + "]");
1420 0 : return form;
1421 0 : }
1422 :
1423 : // Firefly CSR Register
1424 : /// <summary>
1425 : /// Read the TXRX Firefly Present bit
1426 : /// </summary>
1427 : /// <returns>Value of bit</returns>
1428 0 : bool DTCLib::CFOandDTC_Registers::ReadTXRXFireflyPresent(std::optional<uint32_t> val)
1429 : {
1430 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1431 0 : return data[26];
1432 : }
1433 : /// <summary>
1434 : /// Read the RX Firefly Present bit
1435 : /// </summary>
1436 : /// <returns>Value of bit</returns>
1437 0 : bool DTCLib::CFOandDTC_Registers::ReadRXFireflyPresent(std::optional<uint32_t> val)
1438 : {
1439 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1440 0 : return data[25];
1441 : }
1442 : /// <summary>
1443 : /// Read the TX Firefly Present bit
1444 : /// </summary>
1445 : /// <returns>Value of bit</returns>
1446 0 : bool DTCLib::CFOandDTC_Registers::ReadTXFireflyPresent(std::optional<uint32_t> val)
1447 : {
1448 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1449 0 : return data[24];
1450 : }
1451 : /// <summary>
1452 : /// Read the TXRX Firefly Interrupt bit
1453 : /// </summary>
1454 : /// <returns>Value of bit</returns>
1455 0 : bool DTCLib::CFOandDTC_Registers::ReadTXRXFireflyInterrupt(std::optional<uint32_t> val)
1456 : {
1457 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1458 0 : return data[18];
1459 : }
1460 : /// <summary>
1461 : /// Read the RX Firefly Interrupt bit
1462 : /// </summary>
1463 : /// <returns>Value of bit</returns>
1464 0 : bool DTCLib::CFOandDTC_Registers::ReadRXFireflyInterrupt(std::optional<uint32_t> val)
1465 : {
1466 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1467 0 : return data[17];
1468 : }
1469 : /// <summary>
1470 : /// Read the TX Firefly Interrupt bit
1471 : /// </summary>
1472 : /// <returns>Value of bit</returns>
1473 0 : bool DTCLib::CFOandDTC_Registers::ReadTXFireflyInterrupt(std::optional<uint32_t> val)
1474 : {
1475 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1476 0 : return data[16];
1477 : }
1478 : /// <summary>
1479 : /// Read the TXRX Firefly Select bit
1480 : /// </summary>
1481 : /// <returns>Value of bit</returns>
1482 0 : bool DTCLib::CFOandDTC_Registers::ReadTXRXFireflySelect(std::optional<uint32_t> val)
1483 : {
1484 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1485 0 : return data[10];
1486 : }
1487 : /// <summary>
1488 : /// Set the TXRX Firefly Select bit
1489 : /// </summary>
1490 : /// <param name="select">Value to write</param>
1491 0 : void DTCLib::CFOandDTC_Registers::SetTXRXFireflySelect(bool select)
1492 : {
1493 0 : std::bitset<32> data = select << 9; // Do not read value -- ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1494 : // data[9] = select;
1495 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1496 0 : }
1497 : /// <summary>
1498 : /// Read the TX Firefly Select bit
1499 : /// </summary>
1500 : /// <returns>Value of bit</returns>
1501 0 : bool DTCLib::CFOandDTC_Registers::ReadTXFireflySelect(std::optional<uint32_t> val)
1502 : {
1503 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1504 0 : return data[9];
1505 : }
1506 : /// <summary>
1507 : /// Set the TX Firefly Select bit
1508 : /// </summary>
1509 : /// <param name="select">Value to write</param>
1510 0 : void DTCLib::CFOandDTC_Registers::SetTXFireflySelect(bool select)
1511 : {
1512 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1513 0 : data[9] = select;
1514 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1515 0 : }
1516 : /// <summary>
1517 : /// Read the RX Firefly Select bit
1518 : /// </summary>
1519 : /// <returns>Value of bit</returns>
1520 0 : bool DTCLib::CFOandDTC_Registers::ReadRXFireflySelect(std::optional<uint32_t> val)
1521 : {
1522 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1523 0 : return data[8];
1524 : }
1525 : /// <summary>
1526 : /// Set the RX Firefly Select bit
1527 : /// </summary>
1528 : /// <param name="select">Value to write</param>
1529 0 : void DTCLib::CFOandDTC_Registers::SetRXFireflySelect(bool select)
1530 : {
1531 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1532 0 : data[8] = select;
1533 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1534 0 : }
1535 : /// <summary>
1536 : /// Read the TXRX Firefly Reset bit
1537 : /// </summary>
1538 : /// <returns>Value of the bit</returns>
1539 0 : bool DTCLib::CFOandDTC_Registers::ReadResetTXRXFirefly(std::optional<uint32_t> val)
1540 : {
1541 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1542 0 : return data[2];
1543 : }
1544 : /// Reset the TXRX Firefly
1545 0 : void DTCLib::CFOandDTC_Registers::ResetTXRXFirefly()
1546 : {
1547 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1548 0 : data[2] = 1;
1549 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1550 0 : usleep(1000);
1551 0 : data[2] = 0;
1552 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1553 0 : }
1554 : /// <summary>
1555 : /// Read the TX Firefly Reset bit
1556 : /// </summary>
1557 : /// <returns>Value of the bit</returns>
1558 0 : bool DTCLib::CFOandDTC_Registers::ReadResetTXFirefly(std::optional<uint32_t> val)
1559 : {
1560 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1561 0 : return data[1];
1562 : }
1563 : /// Reset the TX Firefly
1564 0 : void DTCLib::CFOandDTC_Registers::ResetTXFirefly()
1565 : {
1566 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1567 0 : data[1] = 1;
1568 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1569 0 : usleep(1000);
1570 0 : data[1] = 0;
1571 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1572 0 : }
1573 : /// <summary>
1574 : /// Read the RX Firefly Reset bit
1575 : /// </summary>
1576 : /// <returns>Value of the bit</returns>
1577 0 : bool DTCLib::CFOandDTC_Registers::ReadResetRXFirefly(std::optional<uint32_t> val)
1578 : {
1579 0 : std::bitset<32> data = val.has_value() ? *val : ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1580 0 : return data[0];
1581 : }
1582 : /// Reset the RX Firefly
1583 0 : void DTCLib::CFOandDTC_Registers::ResetRXFirefly()
1584 : {
1585 0 : std::bitset<32> data = ReadRegister_(CFOandDTC_Register_FireFlyControlStatus);
1586 0 : data[0] = 1;
1587 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1588 0 : usleep(1000);
1589 0 : data[0] = 0;
1590 0 : WriteRegister_(data.to_ulong(), CFOandDTC_Register_FireFlyControlStatus);
1591 0 : }
1592 : /// <summary>
1593 : /// Formats the register's current value for register dumps
1594 : /// </summary>
1595 : /// <returns>RegisterFormatter object containing register information</returns>
1596 0 : DTCLib::RegisterFormatter DTCLib::CFOandDTC_Registers::FormatFireflyCSR()
1597 : {
1598 0 : auto form = CreateFormatter(CFOandDTC_Register_FireFlyControlStatus);
1599 0 : form.description = "FireFly Control and Status";
1600 0 : form.vals.push_back("([ x = 1 (hi) ])"); // translation
1601 0 : form.vals.push_back(std::string("TXRX FireFly Present: [") + (ReadTXRXFireflyPresent(form.value) ? "x" : " ") + "]");
1602 0 : form.vals.push_back(std::string("TX FireFly Present: [") + (ReadRXFireflyPresent(form.value) ? "x" : " ") + "]");
1603 0 : form.vals.push_back(std::string("RX FireFly Present: [") + (ReadTXFireflyPresent(form.value) ? "x" : " ") + "]");
1604 0 : form.vals.push_back(std::string("TXRX FireFly Interrupt: [") + (ReadTXRXFireflyInterrupt(form.value) ? "x" : " ") + "]");
1605 0 : form.vals.push_back(std::string("TX FireFly Interrupt: [") + (ReadRXFireflyInterrupt(form.value) ? "x" : " ") + "]");
1606 0 : form.vals.push_back(std::string("RX FireFly Interrupt: [") + (ReadTXFireflyInterrupt(form.value) ? "x" : " ") + "]");
1607 0 : form.vals.push_back(std::string("TXRX FireFly Select: [") + (ReadTXRXFireflySelect(form.value) ? "x" : " ") + "]");
1608 0 : form.vals.push_back(std::string("TX FireFly Select: [") + (ReadTXFireflySelect(form.value) ? "x" : " ") + "]");
1609 0 : form.vals.push_back(std::string("RX FireFly Select: [") + (ReadRXFireflySelect(form.value) ? "x" : " ") + "]");
1610 0 : form.vals.push_back(std::string("TXRX FireFly Reset: [") + (ReadResetTXRXFirefly(form.value) ? "x" : " ") + "]");
1611 0 : form.vals.push_back(std::string("TX FireFly Reset: [") + (ReadResetTXFirefly(form.value) ? "x" : " ") + "]");
1612 0 : form.vals.push_back(std::string("RX FireFly Reset: [") + (ReadResetRXFirefly(form.value) ? "x" : " ") + "]");
1613 0 : return form;
1614 0 : }
1615 :
1616 : //========================================================================
1617 : /// <summary>
1618 : /// Configure the Jitter Attenuator
1619 : /// </summary>
1620 0 : void DTCLib::CFOandDTC_Registers::ConfigureJitterAttenuator()
1621 : {
1622 0 : CFOandDTC_Register IICLowReg = CFOandDTC_Register_SERDESClock_IICBusLow;
1623 0 : CFOandDTC_Register IICHighReg = CFOandDTC_Register_SERDESClock_IICBusHigh;
1624 :
1625 : // Start configuration preamble
1626 : // set page B
1627 0 : WriteRegister_(0x68010B00, IICLowReg);
1628 0 : WriteRegister_(0x00000001, IICHighReg);
1629 :
1630 : // page B registers
1631 0 : WriteRegister_(0x6824C000, IICLowReg);
1632 0 : WriteRegister_(0x00000001, IICHighReg);
1633 :
1634 0 : WriteRegister_(0x68250000, IICLowReg);
1635 0 : WriteRegister_(0x00000001, IICHighReg);
1636 :
1637 : // set page 5
1638 0 : WriteRegister_(0x68010500, IICLowReg);
1639 0 : WriteRegister_(0x00000001, IICHighReg);
1640 :
1641 : // page 5 registers
1642 0 : WriteRegister_(0x68400100, IICLowReg);
1643 0 : WriteRegister_(0x00000001, IICHighReg);
1644 :
1645 : // End configuration preamble
1646 : //
1647 : // Delay 300 msec
1648 0 : usleep(300000 /*300ms*/);
1649 :
1650 : // Delay is worst case time for device to complete any calibration
1651 : // that is running due to device state change previous to this script
1652 : // being processed.
1653 : //
1654 : // Start configuration registers
1655 : // set page 0
1656 0 : WriteRegister_(0x68010000, IICLowReg);
1657 0 : WriteRegister_(0x00000001, IICHighReg);
1658 :
1659 : // page 0 registers
1660 0 : WriteRegister_(0x68060000, IICLowReg);
1661 0 : WriteRegister_(0x00000001, IICHighReg);
1662 :
1663 0 : WriteRegister_(0x68070000, IICLowReg);
1664 0 : WriteRegister_(0x00000001, IICHighReg);
1665 :
1666 0 : WriteRegister_(0x68080000, IICLowReg);
1667 0 : WriteRegister_(0x00000001, IICHighReg);
1668 :
1669 0 : WriteRegister_(0x680B6800, IICLowReg);
1670 0 : WriteRegister_(0x00000001, IICHighReg);
1671 :
1672 0 : WriteRegister_(0x68160200, IICLowReg);
1673 0 : WriteRegister_(0x00000001, IICHighReg);
1674 :
1675 0 : WriteRegister_(0x6817DC00, IICLowReg);
1676 0 : WriteRegister_(0x00000001, IICHighReg);
1677 :
1678 0 : WriteRegister_(0x68180000, IICLowReg);
1679 0 : WriteRegister_(0x00000001, IICHighReg);
1680 :
1681 0 : WriteRegister_(0x6819DD00, IICLowReg);
1682 0 : WriteRegister_(0x00000001, IICHighReg);
1683 :
1684 0 : WriteRegister_(0x681ADF00, IICLowReg);
1685 0 : WriteRegister_(0x00000001, IICHighReg);
1686 :
1687 0 : WriteRegister_(0x682B0200, IICLowReg);
1688 0 : WriteRegister_(0x00000001, IICHighReg);
1689 :
1690 0 : WriteRegister_(0x682C0F00, IICLowReg);
1691 0 : WriteRegister_(0x00000001, IICHighReg);
1692 :
1693 0 : WriteRegister_(0x682D5500, IICLowReg);
1694 0 : WriteRegister_(0x00000001, IICHighReg);
1695 :
1696 0 : WriteRegister_(0x682E3700, IICLowReg);
1697 0 : WriteRegister_(0x00000001, IICHighReg);
1698 :
1699 0 : WriteRegister_(0x682F0000, IICLowReg);
1700 0 : WriteRegister_(0x00000001, IICHighReg);
1701 :
1702 0 : WriteRegister_(0x68303700, IICLowReg);
1703 0 : WriteRegister_(0x00000001, IICHighReg);
1704 :
1705 0 : WriteRegister_(0x68310000, IICLowReg);
1706 0 : WriteRegister_(0x00000001, IICHighReg);
1707 :
1708 0 : WriteRegister_(0x68323700, IICLowReg);
1709 0 : WriteRegister_(0x00000001, IICHighReg);
1710 :
1711 0 : WriteRegister_(0x68330000, IICLowReg);
1712 0 : WriteRegister_(0x00000001, IICHighReg);
1713 :
1714 0 : WriteRegister_(0x68343700, IICLowReg);
1715 0 : WriteRegister_(0x00000001, IICHighReg);
1716 :
1717 0 : WriteRegister_(0x68350000, IICLowReg);
1718 0 : WriteRegister_(0x00000001, IICHighReg);
1719 :
1720 0 : WriteRegister_(0x68363700, IICLowReg);
1721 0 : WriteRegister_(0x00000001, IICHighReg);
1722 :
1723 0 : WriteRegister_(0x68370000, IICLowReg);
1724 0 : WriteRegister_(0x00000001, IICHighReg);
1725 :
1726 0 : WriteRegister_(0x68383700, IICLowReg);
1727 0 : WriteRegister_(0x00000001, IICHighReg);
1728 :
1729 0 : WriteRegister_(0x68390000, IICLowReg);
1730 0 : WriteRegister_(0x00000001, IICHighReg);
1731 :
1732 0 : WriteRegister_(0x683A3700, IICLowReg);
1733 0 : WriteRegister_(0x00000001, IICHighReg);
1734 :
1735 0 : WriteRegister_(0x683B0000, IICLowReg);
1736 0 : WriteRegister_(0x00000001, IICHighReg);
1737 :
1738 0 : WriteRegister_(0x683C3700, IICLowReg);
1739 0 : WriteRegister_(0x00000001, IICHighReg);
1740 :
1741 0 : WriteRegister_(0x683D0000, IICLowReg);
1742 0 : WriteRegister_(0x00000001, IICHighReg);
1743 :
1744 0 : WriteRegister_(0x683FFF00, IICLowReg);
1745 0 : WriteRegister_(0x00000001, IICHighReg);
1746 :
1747 0 : WriteRegister_(0x68400400, IICLowReg);
1748 0 : WriteRegister_(0x00000001, IICHighReg);
1749 :
1750 0 : WriteRegister_(0x68410E00, IICLowReg);
1751 0 : WriteRegister_(0x00000001, IICHighReg);
1752 :
1753 0 : WriteRegister_(0x68420E00, IICLowReg);
1754 0 : WriteRegister_(0x00000001, IICHighReg);
1755 :
1756 0 : WriteRegister_(0x68430E00, IICLowReg);
1757 0 : WriteRegister_(0x00000001, IICHighReg);
1758 :
1759 0 : WriteRegister_(0x68440E00, IICLowReg);
1760 0 : WriteRegister_(0x00000001, IICHighReg);
1761 :
1762 0 : WriteRegister_(0x68450C00, IICLowReg);
1763 0 : WriteRegister_(0x00000001, IICHighReg);
1764 :
1765 0 : WriteRegister_(0x68463200, IICLowReg);
1766 0 : WriteRegister_(0x00000001, IICHighReg);
1767 :
1768 0 : WriteRegister_(0x68473200, IICLowReg);
1769 0 : WriteRegister_(0x00000001, IICHighReg);
1770 :
1771 0 : WriteRegister_(0x68483200, IICLowReg);
1772 0 : WriteRegister_(0x00000001, IICHighReg);
1773 :
1774 0 : WriteRegister_(0x68493200, IICLowReg);
1775 0 : WriteRegister_(0x00000001, IICHighReg);
1776 :
1777 0 : WriteRegister_(0x684A3200, IICLowReg);
1778 0 : WriteRegister_(0x00000001, IICHighReg);
1779 :
1780 0 : WriteRegister_(0x684B3200, IICLowReg);
1781 0 : WriteRegister_(0x00000001, IICHighReg);
1782 :
1783 0 : WriteRegister_(0x684C3200, IICLowReg);
1784 0 : WriteRegister_(0x00000001, IICHighReg);
1785 :
1786 0 : WriteRegister_(0x684D3200, IICLowReg);
1787 0 : WriteRegister_(0x00000001, IICHighReg);
1788 :
1789 0 : WriteRegister_(0x684E5500, IICLowReg);
1790 0 : WriteRegister_(0x00000001, IICHighReg);
1791 :
1792 0 : WriteRegister_(0x684F5500, IICLowReg);
1793 0 : WriteRegister_(0x00000001, IICHighReg);
1794 :
1795 0 : WriteRegister_(0x68500F00, IICLowReg);
1796 0 : WriteRegister_(0x00000001, IICHighReg);
1797 :
1798 0 : WriteRegister_(0x68510300, IICLowReg);
1799 0 : WriteRegister_(0x00000001, IICHighReg);
1800 :
1801 0 : WriteRegister_(0x68520300, IICLowReg);
1802 0 : WriteRegister_(0x00000001, IICHighReg);
1803 :
1804 0 : WriteRegister_(0x68530300, IICLowReg);
1805 0 : WriteRegister_(0x00000001, IICHighReg);
1806 :
1807 0 : WriteRegister_(0x68540300, IICLowReg);
1808 0 : WriteRegister_(0x00000001, IICHighReg);
1809 :
1810 0 : WriteRegister_(0x68550300, IICLowReg);
1811 0 : WriteRegister_(0x00000001, IICHighReg);
1812 :
1813 0 : WriteRegister_(0x68560300, IICLowReg);
1814 0 : WriteRegister_(0x00000001, IICHighReg);
1815 :
1816 0 : WriteRegister_(0x68570300, IICLowReg);
1817 0 : WriteRegister_(0x00000001, IICHighReg);
1818 :
1819 0 : WriteRegister_(0x68580300, IICLowReg);
1820 0 : WriteRegister_(0x00000001, IICHighReg);
1821 :
1822 0 : WriteRegister_(0x68595500, IICLowReg);
1823 0 : WriteRegister_(0x00000001, IICHighReg);
1824 :
1825 0 : WriteRegister_(0x685AAA00, IICLowReg);
1826 0 : WriteRegister_(0x00000001, IICHighReg);
1827 :
1828 0 : WriteRegister_(0x685BAA00, IICLowReg);
1829 0 : WriteRegister_(0x00000001, IICHighReg);
1830 :
1831 0 : WriteRegister_(0x685C0A00, IICLowReg);
1832 0 : WriteRegister_(0x00000001, IICHighReg);
1833 :
1834 0 : WriteRegister_(0x685D0100, IICLowReg);
1835 0 : WriteRegister_(0x00000001, IICHighReg);
1836 :
1837 0 : WriteRegister_(0x685EAA00, IICLowReg);
1838 0 : WriteRegister_(0x00000001, IICHighReg);
1839 :
1840 0 : WriteRegister_(0x685FAA00, IICLowReg);
1841 0 : WriteRegister_(0x00000001, IICHighReg);
1842 :
1843 0 : WriteRegister_(0x68600A00, IICLowReg);
1844 0 : WriteRegister_(0x00000001, IICHighReg);
1845 :
1846 0 : WriteRegister_(0x68610100, IICLowReg);
1847 0 : WriteRegister_(0x00000001, IICHighReg);
1848 :
1849 0 : WriteRegister_(0x6862AA00, IICLowReg);
1850 0 : WriteRegister_(0x00000001, IICHighReg);
1851 :
1852 0 : WriteRegister_(0x6863AA00, IICLowReg);
1853 0 : WriteRegister_(0x00000001, IICHighReg);
1854 :
1855 0 : WriteRegister_(0x68640A00, IICLowReg);
1856 0 : WriteRegister_(0x00000001, IICHighReg);
1857 :
1858 0 : WriteRegister_(0x68650100, IICLowReg);
1859 0 : WriteRegister_(0x00000001, IICHighReg);
1860 :
1861 0 : WriteRegister_(0x6866AA00, IICLowReg);
1862 0 : WriteRegister_(0x00000001, IICHighReg);
1863 :
1864 0 : WriteRegister_(0x6867AA00, IICLowReg);
1865 0 : WriteRegister_(0x00000001, IICHighReg);
1866 :
1867 0 : WriteRegister_(0x68680A00, IICLowReg);
1868 0 : WriteRegister_(0x00000001, IICHighReg);
1869 :
1870 0 : WriteRegister_(0x68690100, IICLowReg);
1871 0 : WriteRegister_(0x00000001, IICHighReg);
1872 :
1873 0 : WriteRegister_(0x68920200, IICLowReg);
1874 0 : WriteRegister_(0x00000001, IICHighReg);
1875 :
1876 0 : WriteRegister_(0x6893A000, IICLowReg);
1877 0 : WriteRegister_(0x00000001, IICHighReg);
1878 :
1879 0 : WriteRegister_(0x68950000, IICLowReg);
1880 0 : WriteRegister_(0x00000001, IICHighReg);
1881 :
1882 0 : WriteRegister_(0x68968000, IICLowReg);
1883 0 : WriteRegister_(0x00000001, IICHighReg);
1884 :
1885 0 : WriteRegister_(0x68986000, IICLowReg);
1886 0 : WriteRegister_(0x00000001, IICHighReg);
1887 :
1888 0 : WriteRegister_(0x689A0200, IICLowReg);
1889 0 : WriteRegister_(0x00000001, IICHighReg);
1890 :
1891 0 : WriteRegister_(0x689B6000, IICLowReg);
1892 0 : WriteRegister_(0x00000001, IICHighReg);
1893 :
1894 0 : WriteRegister_(0x689D0800, IICLowReg);
1895 0 : WriteRegister_(0x00000001, IICHighReg);
1896 :
1897 0 : WriteRegister_(0x689E4000, IICLowReg);
1898 0 : WriteRegister_(0x00000001, IICHighReg);
1899 :
1900 0 : WriteRegister_(0x68A02000, IICLowReg);
1901 0 : WriteRegister_(0x00000001, IICHighReg);
1902 :
1903 0 : WriteRegister_(0x68A20000, IICLowReg);
1904 0 : WriteRegister_(0x00000001, IICHighReg);
1905 :
1906 0 : WriteRegister_(0x68A98A00, IICLowReg);
1907 0 : WriteRegister_(0x00000001, IICHighReg);
1908 :
1909 0 : WriteRegister_(0x68AA6100, IICLowReg);
1910 0 : WriteRegister_(0x00000001, IICHighReg);
1911 :
1912 0 : WriteRegister_(0x68AB0000, IICLowReg);
1913 0 : WriteRegister_(0x00000001, IICHighReg);
1914 :
1915 0 : WriteRegister_(0x68AC0000, IICLowReg);
1916 0 : WriteRegister_(0x00000001, IICHighReg);
1917 :
1918 0 : WriteRegister_(0x68E52100, IICLowReg);
1919 0 : WriteRegister_(0x00000001, IICHighReg);
1920 :
1921 0 : WriteRegister_(0x68EA0A00, IICLowReg);
1922 0 : WriteRegister_(0x00000001, IICHighReg);
1923 :
1924 0 : WriteRegister_(0x68EB6000, IICLowReg);
1925 0 : WriteRegister_(0x00000001, IICHighReg);
1926 :
1927 0 : WriteRegister_(0x68EC0000, IICLowReg);
1928 0 : WriteRegister_(0x00000001, IICHighReg);
1929 :
1930 0 : WriteRegister_(0x68ED0000, IICLowReg);
1931 0 : WriteRegister_(0x00000001, IICHighReg);
1932 :
1933 : // set page 1
1934 0 : WriteRegister_(0x68010100, IICLowReg);
1935 0 : WriteRegister_(0x00000001, IICHighReg);
1936 :
1937 : // page 1 registers
1938 0 : WriteRegister_(0x68020100, IICLowReg);
1939 0 : WriteRegister_(0x00000001, IICHighReg);
1940 :
1941 0 : WriteRegister_(0x68120600, IICLowReg);
1942 0 : WriteRegister_(0x00000001, IICHighReg);
1943 :
1944 0 : WriteRegister_(0x68130900, IICLowReg);
1945 0 : WriteRegister_(0x00000001, IICHighReg);
1946 :
1947 0 : WriteRegister_(0x68143B00, IICLowReg);
1948 0 : WriteRegister_(0x00000001, IICHighReg);
1949 :
1950 0 : WriteRegister_(0x68152800, IICLowReg);
1951 0 : WriteRegister_(0x00000001, IICHighReg);
1952 :
1953 0 : WriteRegister_(0x68170600, IICLowReg);
1954 0 : WriteRegister_(0x00000001, IICHighReg);
1955 :
1956 0 : WriteRegister_(0x68180900, IICLowReg);
1957 0 : WriteRegister_(0x00000001, IICHighReg);
1958 :
1959 0 : WriteRegister_(0x68193B00, IICLowReg);
1960 0 : WriteRegister_(0x00000001, IICHighReg);
1961 :
1962 0 : WriteRegister_(0x681A2800, IICLowReg);
1963 0 : WriteRegister_(0x00000001, IICHighReg);
1964 :
1965 0 : WriteRegister_(0x683F1000, IICLowReg);
1966 0 : WriteRegister_(0x00000001, IICHighReg);
1967 :
1968 0 : WriteRegister_(0x68400000, IICLowReg);
1969 0 : WriteRegister_(0x00000001, IICHighReg);
1970 :
1971 0 : WriteRegister_(0x68414000, IICLowReg);
1972 0 : WriteRegister_(0x00000001, IICHighReg);
1973 :
1974 0 : WriteRegister_(0x6842FF00, IICLowReg);
1975 0 : WriteRegister_(0x00000001, IICHighReg);
1976 :
1977 : // set page 2
1978 0 : WriteRegister_(0x68010200, IICLowReg);
1979 0 : WriteRegister_(0x00000001, IICHighReg);
1980 :
1981 : // page 2 registers
1982 0 : WriteRegister_(0x68060000, IICLowReg);
1983 0 : WriteRegister_(0x00000001, IICHighReg);
1984 :
1985 0 : WriteRegister_(0x68086400, IICLowReg);
1986 0 : WriteRegister_(0x00000001, IICHighReg);
1987 :
1988 0 : WriteRegister_(0x68090000, IICLowReg);
1989 0 : WriteRegister_(0x00000001, IICHighReg);
1990 :
1991 0 : WriteRegister_(0x680A0000, IICLowReg);
1992 0 : WriteRegister_(0x00000001, IICHighReg);
1993 :
1994 0 : WriteRegister_(0x680B0000, IICLowReg);
1995 0 : WriteRegister_(0x00000001, IICHighReg);
1996 :
1997 0 : WriteRegister_(0x680C0000, IICLowReg);
1998 0 : WriteRegister_(0x00000001, IICHighReg);
1999 :
2000 0 : WriteRegister_(0x680D0000, IICLowReg);
2001 0 : WriteRegister_(0x00000001, IICHighReg);
2002 :
2003 0 : WriteRegister_(0x680E0100, IICLowReg);
2004 0 : WriteRegister_(0x00000001, IICHighReg);
2005 :
2006 0 : WriteRegister_(0x680F0000, IICLowReg);
2007 0 : WriteRegister_(0x00000001, IICHighReg);
2008 :
2009 0 : WriteRegister_(0x68100000, IICLowReg);
2010 0 : WriteRegister_(0x00000001, IICHighReg);
2011 :
2012 0 : WriteRegister_(0x68110000, IICLowReg);
2013 0 : WriteRegister_(0x00000001, IICHighReg);
2014 :
2015 0 : WriteRegister_(0x68126400, IICLowReg);
2016 0 : WriteRegister_(0x00000001, IICHighReg);
2017 :
2018 0 : WriteRegister_(0x68130000, IICLowReg);
2019 0 : WriteRegister_(0x00000001, IICHighReg);
2020 :
2021 0 : WriteRegister_(0x68140000, IICLowReg);
2022 0 : WriteRegister_(0x00000001, IICHighReg);
2023 :
2024 0 : WriteRegister_(0x68150000, IICLowReg);
2025 0 : WriteRegister_(0x00000001, IICHighReg);
2026 :
2027 0 : WriteRegister_(0x68160000, IICLowReg);
2028 0 : WriteRegister_(0x00000001, IICHighReg);
2029 :
2030 0 : WriteRegister_(0x68170000, IICLowReg);
2031 0 : WriteRegister_(0x00000001, IICHighReg);
2032 :
2033 0 : WriteRegister_(0x68180100, IICLowReg);
2034 0 : WriteRegister_(0x00000001, IICHighReg);
2035 :
2036 0 : WriteRegister_(0x68190000, IICLowReg);
2037 0 : WriteRegister_(0x00000001, IICHighReg);
2038 :
2039 0 : WriteRegister_(0x681A0000, IICLowReg);
2040 0 : WriteRegister_(0x00000001, IICHighReg);
2041 :
2042 0 : WriteRegister_(0x681B0000, IICLowReg);
2043 0 : WriteRegister_(0x00000001, IICHighReg);
2044 :
2045 0 : WriteRegister_(0x681C6400, IICLowReg);
2046 0 : WriteRegister_(0x00000001, IICHighReg);
2047 :
2048 0 : WriteRegister_(0x681D0000, IICLowReg);
2049 0 : WriteRegister_(0x00000001, IICHighReg);
2050 :
2051 0 : WriteRegister_(0x681E0000, IICLowReg);
2052 0 : WriteRegister_(0x00000001, IICHighReg);
2053 :
2054 0 : WriteRegister_(0x681F0000, IICLowReg);
2055 0 : WriteRegister_(0x00000001, IICHighReg);
2056 :
2057 0 : WriteRegister_(0x68200000, IICLowReg);
2058 0 : WriteRegister_(0x00000001, IICHighReg);
2059 :
2060 0 : WriteRegister_(0x68210000, IICLowReg);
2061 0 : WriteRegister_(0x00000001, IICHighReg);
2062 :
2063 0 : WriteRegister_(0x68220100, IICLowReg);
2064 0 : WriteRegister_(0x00000001, IICHighReg);
2065 :
2066 0 : WriteRegister_(0x68230000, IICLowReg);
2067 0 : WriteRegister_(0x00000001, IICHighReg);
2068 :
2069 0 : WriteRegister_(0x68240000, IICLowReg);
2070 0 : WriteRegister_(0x00000001, IICHighReg);
2071 :
2072 0 : WriteRegister_(0x68250000, IICLowReg);
2073 0 : WriteRegister_(0x00000001, IICHighReg);
2074 :
2075 0 : WriteRegister_(0x68266400, IICLowReg);
2076 0 : WriteRegister_(0x00000001, IICHighReg);
2077 :
2078 0 : WriteRegister_(0x68270000, IICLowReg);
2079 0 : WriteRegister_(0x00000001, IICHighReg);
2080 :
2081 0 : WriteRegister_(0x68280000, IICLowReg);
2082 0 : WriteRegister_(0x00000001, IICHighReg);
2083 :
2084 0 : WriteRegister_(0x68290000, IICLowReg);
2085 0 : WriteRegister_(0x00000001, IICHighReg);
2086 :
2087 0 : WriteRegister_(0x682A0000, IICLowReg);
2088 0 : WriteRegister_(0x00000001, IICHighReg);
2089 :
2090 0 : WriteRegister_(0x682B0000, IICLowReg);
2091 0 : WriteRegister_(0x00000001, IICHighReg);
2092 :
2093 0 : WriteRegister_(0x682C0100, IICLowReg);
2094 0 : WriteRegister_(0x00000001, IICHighReg);
2095 :
2096 0 : WriteRegister_(0x682D0000, IICLowReg);
2097 0 : WriteRegister_(0x00000001, IICHighReg);
2098 :
2099 0 : WriteRegister_(0x682E0000, IICLowReg);
2100 0 : WriteRegister_(0x00000001, IICHighReg);
2101 :
2102 0 : WriteRegister_(0x682F0000, IICLowReg);
2103 0 : WriteRegister_(0x00000001, IICHighReg);
2104 :
2105 0 : WriteRegister_(0x68310B00, IICLowReg);
2106 0 : WriteRegister_(0x00000001, IICHighReg);
2107 :
2108 0 : WriteRegister_(0x68320B00, IICLowReg);
2109 0 : WriteRegister_(0x00000001, IICHighReg);
2110 :
2111 0 : WriteRegister_(0x68330B00, IICLowReg);
2112 0 : WriteRegister_(0x00000001, IICHighReg);
2113 :
2114 0 : WriteRegister_(0x68340B00, IICLowReg);
2115 0 : WriteRegister_(0x00000001, IICHighReg);
2116 :
2117 0 : WriteRegister_(0x68350000, IICLowReg);
2118 0 : WriteRegister_(0x00000001, IICHighReg);
2119 :
2120 0 : WriteRegister_(0x68360000, IICLowReg);
2121 0 : WriteRegister_(0x00000001, IICHighReg);
2122 :
2123 0 : WriteRegister_(0x68370000, IICLowReg);
2124 0 : WriteRegister_(0x00000001, IICHighReg);
2125 :
2126 0 : WriteRegister_(0x68388000, IICLowReg);
2127 0 : WriteRegister_(0x00000001, IICHighReg);
2128 :
2129 0 : WriteRegister_(0x6839D400, IICLowReg);
2130 0 : WriteRegister_(0x00000001, IICHighReg);
2131 :
2132 0 : WriteRegister_(0x683A0000, IICLowReg);
2133 0 : WriteRegister_(0x00000001, IICHighReg);
2134 :
2135 0 : WriteRegister_(0x683B0000, IICLowReg);
2136 0 : WriteRegister_(0x00000001, IICHighReg);
2137 :
2138 0 : WriteRegister_(0x683C0000, IICLowReg);
2139 0 : WriteRegister_(0x00000001, IICHighReg);
2140 :
2141 0 : WriteRegister_(0x683D0000, IICLowReg);
2142 0 : WriteRegister_(0x00000001, IICHighReg);
2143 :
2144 0 : WriteRegister_(0x683EC000, IICLowReg);
2145 0 : WriteRegister_(0x00000001, IICHighReg);
2146 :
2147 0 : WriteRegister_(0x68500000, IICLowReg);
2148 0 : WriteRegister_(0x00000001, IICHighReg);
2149 :
2150 0 : WriteRegister_(0x68510000, IICLowReg);
2151 0 : WriteRegister_(0x00000001, IICHighReg);
2152 :
2153 0 : WriteRegister_(0x68520000, IICLowReg);
2154 0 : WriteRegister_(0x00000001, IICHighReg);
2155 :
2156 0 : WriteRegister_(0x68530000, IICLowReg);
2157 0 : WriteRegister_(0x00000001, IICHighReg);
2158 :
2159 0 : WriteRegister_(0x68540000, IICLowReg);
2160 0 : WriteRegister_(0x00000001, IICHighReg);
2161 :
2162 0 : WriteRegister_(0x68550000, IICLowReg);
2163 0 : WriteRegister_(0x00000001, IICHighReg);
2164 :
2165 0 : WriteRegister_(0x686B5200, IICLowReg);
2166 0 : WriteRegister_(0x00000001, IICHighReg);
2167 :
2168 0 : WriteRegister_(0x686C6500, IICLowReg);
2169 0 : WriteRegister_(0x00000001, IICHighReg);
2170 :
2171 0 : WriteRegister_(0x686D7600, IICLowReg);
2172 0 : WriteRegister_(0x00000001, IICHighReg);
2173 :
2174 0 : WriteRegister_(0x686E3100, IICLowReg);
2175 0 : WriteRegister_(0x00000001, IICHighReg);
2176 :
2177 0 : WriteRegister_(0x686F2000, IICLowReg);
2178 0 : WriteRegister_(0x00000001, IICHighReg);
2179 :
2180 0 : WriteRegister_(0x68702000, IICLowReg);
2181 0 : WriteRegister_(0x00000001, IICHighReg);
2182 :
2183 0 : WriteRegister_(0x68712000, IICLowReg);
2184 0 : WriteRegister_(0x00000001, IICHighReg);
2185 :
2186 0 : WriteRegister_(0x68722000, IICLowReg);
2187 0 : WriteRegister_(0x00000001, IICHighReg);
2188 :
2189 0 : WriteRegister_(0x688A0000, IICLowReg);
2190 0 : WriteRegister_(0x00000001, IICHighReg);
2191 :
2192 0 : WriteRegister_(0x688B0000, IICLowReg);
2193 0 : WriteRegister_(0x00000001, IICHighReg);
2194 :
2195 0 : WriteRegister_(0x688C0000, IICLowReg);
2196 0 : WriteRegister_(0x00000001, IICHighReg);
2197 :
2198 0 : WriteRegister_(0x688D0000, IICLowReg);
2199 0 : WriteRegister_(0x00000001, IICHighReg);
2200 :
2201 0 : WriteRegister_(0x688E0000, IICLowReg);
2202 0 : WriteRegister_(0x00000001, IICHighReg);
2203 :
2204 0 : WriteRegister_(0x688F0000, IICLowReg);
2205 0 : WriteRegister_(0x00000001, IICHighReg);
2206 :
2207 0 : WriteRegister_(0x68900000, IICLowReg);
2208 0 : WriteRegister_(0x00000001, IICHighReg);
2209 :
2210 0 : WriteRegister_(0x68910000, IICLowReg);
2211 0 : WriteRegister_(0x00000001, IICHighReg);
2212 :
2213 0 : WriteRegister_(0x6894B000, IICLowReg);
2214 0 : WriteRegister_(0x00000001, IICHighReg);
2215 :
2216 0 : WriteRegister_(0x68960200, IICLowReg);
2217 0 : WriteRegister_(0x00000001, IICHighReg);
2218 :
2219 0 : WriteRegister_(0x68970200, IICLowReg);
2220 0 : WriteRegister_(0x00000001, IICHighReg);
2221 :
2222 0 : WriteRegister_(0x68990200, IICLowReg);
2223 0 : WriteRegister_(0x00000001, IICHighReg);
2224 :
2225 0 : WriteRegister_(0x689DFA00, IICLowReg);
2226 0 : WriteRegister_(0x00000001, IICHighReg);
2227 :
2228 0 : WriteRegister_(0x689E0100, IICLowReg);
2229 0 : WriteRegister_(0x00000001, IICHighReg);
2230 :
2231 0 : WriteRegister_(0x689F0000, IICLowReg);
2232 0 : WriteRegister_(0x00000001, IICHighReg);
2233 :
2234 0 : WriteRegister_(0x68A9CC00, IICLowReg);
2235 0 : WriteRegister_(0x00000001, IICHighReg);
2236 :
2237 0 : WriteRegister_(0x68AA0400, IICLowReg);
2238 0 : WriteRegister_(0x00000001, IICHighReg);
2239 :
2240 0 : WriteRegister_(0x68AB0000, IICLowReg);
2241 0 : WriteRegister_(0x00000001, IICHighReg);
2242 :
2243 0 : WriteRegister_(0x68B7FF00, IICLowReg);
2244 0 : WriteRegister_(0x00000001, IICHighReg);
2245 :
2246 : // set page 3
2247 0 : WriteRegister_(0x68010300, IICLowReg);
2248 0 : WriteRegister_(0x00000001, IICHighReg);
2249 :
2250 : // page 3 registers
2251 0 : WriteRegister_(0x68020000, IICLowReg);
2252 0 : WriteRegister_(0x00000001, IICHighReg);
2253 :
2254 0 : WriteRegister_(0x68030000, IICLowReg);
2255 0 : WriteRegister_(0x00000001, IICHighReg);
2256 :
2257 0 : WriteRegister_(0x68040000, IICLowReg);
2258 0 : WriteRegister_(0x00000001, IICHighReg);
2259 :
2260 0 : WriteRegister_(0x68050000, IICLowReg);
2261 0 : WriteRegister_(0x00000001, IICHighReg);
2262 :
2263 0 : WriteRegister_(0x68061100, IICLowReg);
2264 0 : WriteRegister_(0x00000001, IICHighReg);
2265 :
2266 0 : WriteRegister_(0x68070000, IICLowReg);
2267 0 : WriteRegister_(0x00000001, IICHighReg);
2268 :
2269 0 : WriteRegister_(0x68080000, IICLowReg);
2270 0 : WriteRegister_(0x00000001, IICHighReg);
2271 :
2272 0 : WriteRegister_(0x68090000, IICLowReg);
2273 0 : WriteRegister_(0x00000001, IICHighReg);
2274 :
2275 0 : WriteRegister_(0x680A0000, IICLowReg);
2276 0 : WriteRegister_(0x00000001, IICHighReg);
2277 :
2278 0 : WriteRegister_(0x680B8000, IICLowReg);
2279 0 : WriteRegister_(0x00000001, IICHighReg);
2280 :
2281 0 : WriteRegister_(0x680C0000, IICLowReg);
2282 0 : WriteRegister_(0x00000001, IICHighReg);
2283 :
2284 0 : WriteRegister_(0x680D0000, IICLowReg);
2285 0 : WriteRegister_(0x00000001, IICHighReg);
2286 :
2287 0 : WriteRegister_(0x680E0000, IICLowReg);
2288 0 : WriteRegister_(0x00000001, IICHighReg);
2289 :
2290 0 : WriteRegister_(0x680F0000, IICLowReg);
2291 0 : WriteRegister_(0x00000001, IICHighReg);
2292 :
2293 0 : WriteRegister_(0x68100000, IICLowReg);
2294 0 : WriteRegister_(0x00000001, IICHighReg);
2295 :
2296 0 : WriteRegister_(0x68110000, IICLowReg);
2297 0 : WriteRegister_(0x00000001, IICHighReg);
2298 :
2299 0 : WriteRegister_(0x68120000, IICLowReg);
2300 0 : WriteRegister_(0x00000001, IICHighReg);
2301 :
2302 0 : WriteRegister_(0x68130000, IICLowReg);
2303 0 : WriteRegister_(0x00000001, IICHighReg);
2304 :
2305 0 : WriteRegister_(0x68140000, IICLowReg);
2306 0 : WriteRegister_(0x00000001, IICHighReg);
2307 :
2308 0 : WriteRegister_(0x68150000, IICLowReg);
2309 0 : WriteRegister_(0x00000001, IICHighReg);
2310 :
2311 0 : WriteRegister_(0x68160000, IICLowReg);
2312 0 : WriteRegister_(0x00000001, IICHighReg);
2313 :
2314 0 : WriteRegister_(0x68170000, IICLowReg);
2315 0 : WriteRegister_(0x00000001, IICHighReg);
2316 :
2317 0 : WriteRegister_(0x68380000, IICLowReg);
2318 0 : WriteRegister_(0x00000001, IICHighReg);
2319 :
2320 0 : WriteRegister_(0x68391F00, IICLowReg);
2321 0 : WriteRegister_(0x00000001, IICHighReg);
2322 :
2323 0 : WriteRegister_(0x683B0000, IICLowReg);
2324 0 : WriteRegister_(0x00000001, IICHighReg);
2325 :
2326 0 : WriteRegister_(0x683C0000, IICLowReg);
2327 0 : WriteRegister_(0x00000001, IICHighReg);
2328 :
2329 0 : WriteRegister_(0x683D0000, IICLowReg);
2330 0 : WriteRegister_(0x00000001, IICHighReg);
2331 :
2332 0 : WriteRegister_(0x683E0000, IICLowReg);
2333 0 : WriteRegister_(0x00000001, IICHighReg);
2334 :
2335 0 : WriteRegister_(0x683F0000, IICLowReg);
2336 0 : WriteRegister_(0x00000001, IICHighReg);
2337 :
2338 0 : WriteRegister_(0x68400000, IICLowReg);
2339 0 : WriteRegister_(0x00000001, IICHighReg);
2340 :
2341 0 : WriteRegister_(0x68410000, IICLowReg);
2342 0 : WriteRegister_(0x00000001, IICHighReg);
2343 :
2344 0 : WriteRegister_(0x68420000, IICLowReg);
2345 0 : WriteRegister_(0x00000001, IICHighReg);
2346 :
2347 0 : WriteRegister_(0x68430000, IICLowReg);
2348 0 : WriteRegister_(0x00000001, IICHighReg);
2349 :
2350 0 : WriteRegister_(0x68440000, IICLowReg);
2351 0 : WriteRegister_(0x00000001, IICHighReg);
2352 :
2353 0 : WriteRegister_(0x68450000, IICLowReg);
2354 0 : WriteRegister_(0x00000001, IICHighReg);
2355 :
2356 0 : WriteRegister_(0x68460000, IICLowReg);
2357 0 : WriteRegister_(0x00000001, IICHighReg);
2358 :
2359 0 : WriteRegister_(0x68590000, IICLowReg);
2360 0 : WriteRegister_(0x00000001, IICHighReg);
2361 :
2362 0 : WriteRegister_(0x685A0000, IICLowReg);
2363 0 : WriteRegister_(0x00000001, IICHighReg);
2364 :
2365 0 : WriteRegister_(0x685B0000, IICLowReg);
2366 0 : WriteRegister_(0x00000001, IICHighReg);
2367 :
2368 0 : WriteRegister_(0x685C0000, IICLowReg);
2369 0 : WriteRegister_(0x00000001, IICHighReg);
2370 :
2371 : // set page 4
2372 0 : WriteRegister_(0x68010400, IICLowReg);
2373 0 : WriteRegister_(0x00000001, IICHighReg);
2374 :
2375 : // page 4 registers
2376 0 : WriteRegister_(0x68870100, IICLowReg);
2377 0 : WriteRegister_(0x00000001, IICHighReg);
2378 :
2379 : // set page 5
2380 0 : WriteRegister_(0x68010500, IICLowReg);
2381 0 : WriteRegister_(0x00000001, IICHighReg);
2382 :
2383 : // page 5 registers
2384 0 : WriteRegister_(0x68081000, IICLowReg);
2385 0 : WriteRegister_(0x00000001, IICHighReg);
2386 :
2387 0 : WriteRegister_(0x68091F00, IICLowReg);
2388 0 : WriteRegister_(0x00000001, IICHighReg);
2389 :
2390 0 : WriteRegister_(0x680A0C00, IICLowReg);
2391 0 : WriteRegister_(0x00000001, IICHighReg);
2392 :
2393 0 : WriteRegister_(0x680B0B00, IICLowReg);
2394 0 : WriteRegister_(0x00000001, IICHighReg);
2395 :
2396 0 : WriteRegister_(0x680C3F00, IICLowReg);
2397 0 : WriteRegister_(0x00000001, IICHighReg);
2398 :
2399 0 : WriteRegister_(0x680D3F00, IICLowReg);
2400 0 : WriteRegister_(0x00000001, IICHighReg);
2401 :
2402 0 : WriteRegister_(0x680E1300, IICLowReg);
2403 0 : WriteRegister_(0x00000001, IICHighReg);
2404 :
2405 0 : WriteRegister_(0x680F2700, IICLowReg);
2406 0 : WriteRegister_(0x00000001, IICHighReg);
2407 :
2408 0 : WriteRegister_(0x68100900, IICLowReg);
2409 0 : WriteRegister_(0x00000001, IICHighReg);
2410 :
2411 0 : WriteRegister_(0x68110800, IICLowReg);
2412 0 : WriteRegister_(0x00000001, IICHighReg);
2413 :
2414 0 : WriteRegister_(0x68123F00, IICLowReg);
2415 0 : WriteRegister_(0x00000001, IICHighReg);
2416 :
2417 0 : WriteRegister_(0x68133F00, IICLowReg);
2418 0 : WriteRegister_(0x00000001, IICHighReg);
2419 :
2420 0 : WriteRegister_(0x68150000, IICLowReg);
2421 0 : WriteRegister_(0x00000001, IICHighReg);
2422 :
2423 0 : WriteRegister_(0x68160000, IICLowReg);
2424 0 : WriteRegister_(0x00000001, IICHighReg);
2425 :
2426 0 : WriteRegister_(0x68170000, IICLowReg);
2427 0 : WriteRegister_(0x00000001, IICHighReg);
2428 :
2429 0 : WriteRegister_(0x68180000, IICLowReg);
2430 0 : WriteRegister_(0x00000001, IICHighReg);
2431 :
2432 0 : WriteRegister_(0x6819A800, IICLowReg);
2433 0 : WriteRegister_(0x00000001, IICHighReg);
2434 :
2435 0 : WriteRegister_(0x681A0200, IICLowReg);
2436 0 : WriteRegister_(0x00000001, IICHighReg);
2437 :
2438 0 : WriteRegister_(0x681B0000, IICLowReg);
2439 0 : WriteRegister_(0x00000001, IICHighReg);
2440 :
2441 0 : WriteRegister_(0x681C0000, IICLowReg);
2442 0 : WriteRegister_(0x00000001, IICHighReg);
2443 :
2444 0 : WriteRegister_(0x681D0000, IICLowReg);
2445 0 : WriteRegister_(0x00000001, IICHighReg);
2446 :
2447 0 : WriteRegister_(0x681E0000, IICLowReg);
2448 0 : WriteRegister_(0x00000001, IICHighReg);
2449 :
2450 0 : WriteRegister_(0x681F8000, IICLowReg);
2451 0 : WriteRegister_(0x00000001, IICHighReg);
2452 :
2453 0 : WriteRegister_(0x68212B00, IICLowReg);
2454 0 : WriteRegister_(0x00000001, IICHighReg);
2455 :
2456 0 : WriteRegister_(0x682A0000, IICLowReg);
2457 0 : WriteRegister_(0x00000001, IICHighReg);
2458 :
2459 0 : WriteRegister_(0x682B0100, IICLowReg);
2460 0 : WriteRegister_(0x00000001, IICHighReg);
2461 :
2462 0 : WriteRegister_(0x682C8700, IICLowReg);
2463 0 : WriteRegister_(0x00000001, IICHighReg);
2464 :
2465 0 : WriteRegister_(0x682D0300, IICLowReg);
2466 0 : WriteRegister_(0x00000001, IICHighReg);
2467 :
2468 0 : WriteRegister_(0x682E1900, IICLowReg);
2469 0 : WriteRegister_(0x00000001, IICHighReg);
2470 :
2471 0 : WriteRegister_(0x682F1900, IICLowReg);
2472 0 : WriteRegister_(0x00000001, IICHighReg);
2473 :
2474 0 : WriteRegister_(0x68310000, IICLowReg);
2475 0 : WriteRegister_(0x00000001, IICHighReg);
2476 :
2477 0 : WriteRegister_(0x68324200, IICLowReg);
2478 0 : WriteRegister_(0x00000001, IICHighReg);
2479 :
2480 0 : WriteRegister_(0x68330300, IICLowReg);
2481 0 : WriteRegister_(0x00000001, IICHighReg);
2482 :
2483 0 : WriteRegister_(0x68340000, IICLowReg);
2484 0 : WriteRegister_(0x00000001, IICHighReg);
2485 :
2486 0 : WriteRegister_(0x68350000, IICLowReg);
2487 0 : WriteRegister_(0x00000001, IICHighReg);
2488 :
2489 0 : WriteRegister_(0x68360000, IICLowReg);
2490 0 : WriteRegister_(0x00000001, IICHighReg);
2491 :
2492 0 : WriteRegister_(0x68370000, IICLowReg);
2493 0 : WriteRegister_(0x00000001, IICHighReg);
2494 :
2495 0 : WriteRegister_(0x68380000, IICLowReg);
2496 0 : WriteRegister_(0x00000001, IICHighReg);
2497 :
2498 0 : WriteRegister_(0x68390000, IICLowReg);
2499 0 : WriteRegister_(0x00000001, IICHighReg);
2500 :
2501 0 : WriteRegister_(0x683A0200, IICLowReg);
2502 0 : WriteRegister_(0x00000001, IICHighReg);
2503 :
2504 0 : WriteRegister_(0x683B0300, IICLowReg);
2505 0 : WriteRegister_(0x00000001, IICHighReg);
2506 :
2507 0 : WriteRegister_(0x683C0000, IICLowReg);
2508 0 : WriteRegister_(0x00000001, IICHighReg);
2509 :
2510 0 : WriteRegister_(0x683D1100, IICLowReg);
2511 0 : WriteRegister_(0x00000001, IICHighReg);
2512 :
2513 0 : WriteRegister_(0x683E0600, IICLowReg);
2514 0 : WriteRegister_(0x00000001, IICHighReg);
2515 :
2516 0 : WriteRegister_(0x68890D00, IICLowReg);
2517 0 : WriteRegister_(0x00000001, IICHighReg);
2518 :
2519 0 : WriteRegister_(0x688A0000, IICLowReg);
2520 0 : WriteRegister_(0x00000001, IICHighReg);
2521 :
2522 0 : WriteRegister_(0x689BFA00, IICLowReg);
2523 0 : WriteRegister_(0x00000001, IICHighReg);
2524 :
2525 0 : WriteRegister_(0x689D1000, IICLowReg);
2526 0 : WriteRegister_(0x00000001, IICHighReg);
2527 :
2528 0 : WriteRegister_(0x689E2100, IICLowReg);
2529 0 : WriteRegister_(0x00000001, IICHighReg);
2530 :
2531 0 : WriteRegister_(0x689F0C00, IICLowReg);
2532 0 : WriteRegister_(0x00000001, IICHighReg);
2533 :
2534 0 : WriteRegister_(0x68A00B00, IICLowReg);
2535 0 : WriteRegister_(0x00000001, IICHighReg);
2536 :
2537 0 : WriteRegister_(0x68A13F00, IICLowReg);
2538 0 : WriteRegister_(0x00000001, IICHighReg);
2539 :
2540 0 : WriteRegister_(0x68A23F00, IICLowReg);
2541 0 : WriteRegister_(0x00000001, IICHighReg);
2542 :
2543 0 : WriteRegister_(0x68A60300, IICLowReg);
2544 0 : WriteRegister_(0x00000001, IICHighReg);
2545 :
2546 : // set page 8
2547 0 : WriteRegister_(0x68010800, IICLowReg);
2548 0 : WriteRegister_(0x00000001, IICHighReg);
2549 :
2550 : // page 8 registers
2551 0 : WriteRegister_(0x68023500, IICLowReg);
2552 0 : WriteRegister_(0x00000001, IICHighReg);
2553 :
2554 0 : WriteRegister_(0x68030500, IICLowReg);
2555 0 : WriteRegister_(0x00000001, IICHighReg);
2556 :
2557 0 : WriteRegister_(0x68040000, IICLowReg);
2558 0 : WriteRegister_(0x00000001, IICHighReg);
2559 :
2560 0 : WriteRegister_(0x68050000, IICLowReg);
2561 0 : WriteRegister_(0x00000001, IICHighReg);
2562 :
2563 0 : WriteRegister_(0x68060000, IICLowReg);
2564 0 : WriteRegister_(0x00000001, IICHighReg);
2565 :
2566 0 : WriteRegister_(0x68070000, IICLowReg);
2567 0 : WriteRegister_(0x00000001, IICHighReg);
2568 :
2569 0 : WriteRegister_(0x68080000, IICLowReg);
2570 0 : WriteRegister_(0x00000001, IICHighReg);
2571 :
2572 0 : WriteRegister_(0x68090000, IICLowReg);
2573 0 : WriteRegister_(0x00000001, IICHighReg);
2574 :
2575 0 : WriteRegister_(0x680A0000, IICLowReg);
2576 0 : WriteRegister_(0x00000001, IICHighReg);
2577 :
2578 0 : WriteRegister_(0x680B0000, IICLowReg);
2579 0 : WriteRegister_(0x00000001, IICHighReg);
2580 :
2581 0 : WriteRegister_(0x680C0000, IICLowReg);
2582 0 : WriteRegister_(0x00000001, IICHighReg);
2583 :
2584 0 : WriteRegister_(0x680D0000, IICLowReg);
2585 0 : WriteRegister_(0x00000001, IICHighReg);
2586 :
2587 0 : WriteRegister_(0x680E0000, IICLowReg);
2588 0 : WriteRegister_(0x00000001, IICHighReg);
2589 :
2590 0 : WriteRegister_(0x680F0000, IICLowReg);
2591 0 : WriteRegister_(0x00000001, IICHighReg);
2592 :
2593 0 : WriteRegister_(0x68100000, IICLowReg);
2594 0 : WriteRegister_(0x00000001, IICHighReg);
2595 :
2596 0 : WriteRegister_(0x68110000, IICLowReg);
2597 0 : WriteRegister_(0x00000001, IICHighReg);
2598 :
2599 0 : WriteRegister_(0x68120000, IICLowReg);
2600 0 : WriteRegister_(0x00000001, IICHighReg);
2601 :
2602 0 : WriteRegister_(0x68130000, IICLowReg);
2603 0 : WriteRegister_(0x00000001, IICHighReg);
2604 :
2605 0 : WriteRegister_(0x68140000, IICLowReg);
2606 0 : WriteRegister_(0x00000001, IICHighReg);
2607 :
2608 0 : WriteRegister_(0x68150000, IICLowReg);
2609 0 : WriteRegister_(0x00000001, IICHighReg);
2610 :
2611 0 : WriteRegister_(0x68160000, IICLowReg);
2612 0 : WriteRegister_(0x00000001, IICHighReg);
2613 :
2614 0 : WriteRegister_(0x68170000, IICLowReg);
2615 0 : WriteRegister_(0x00000001, IICHighReg);
2616 :
2617 0 : WriteRegister_(0x68180000, IICLowReg);
2618 0 : WriteRegister_(0x00000001, IICHighReg);
2619 :
2620 0 : WriteRegister_(0x68190000, IICLowReg);
2621 0 : WriteRegister_(0x00000001, IICHighReg);
2622 :
2623 0 : WriteRegister_(0x681A0000, IICLowReg);
2624 0 : WriteRegister_(0x00000001, IICHighReg);
2625 :
2626 0 : WriteRegister_(0x681B0000, IICLowReg);
2627 0 : WriteRegister_(0x00000001, IICHighReg);
2628 :
2629 0 : WriteRegister_(0x681C0000, IICLowReg);
2630 0 : WriteRegister_(0x00000001, IICHighReg);
2631 :
2632 0 : WriteRegister_(0x681D0000, IICLowReg);
2633 0 : WriteRegister_(0x00000001, IICHighReg);
2634 :
2635 0 : WriteRegister_(0x681E0000, IICLowReg);
2636 0 : WriteRegister_(0x00000001, IICHighReg);
2637 :
2638 0 : WriteRegister_(0x681F0000, IICLowReg);
2639 0 : WriteRegister_(0x00000001, IICHighReg);
2640 :
2641 0 : WriteRegister_(0x68200000, IICLowReg);
2642 0 : WriteRegister_(0x00000001, IICHighReg);
2643 :
2644 0 : WriteRegister_(0x68210000, IICLowReg);
2645 0 : WriteRegister_(0x00000001, IICHighReg);
2646 :
2647 0 : WriteRegister_(0x68220000, IICLowReg);
2648 0 : WriteRegister_(0x00000001, IICHighReg);
2649 :
2650 0 : WriteRegister_(0x68230000, IICLowReg);
2651 0 : WriteRegister_(0x00000001, IICHighReg);
2652 :
2653 0 : WriteRegister_(0x68240000, IICLowReg);
2654 0 : WriteRegister_(0x00000001, IICHighReg);
2655 :
2656 0 : WriteRegister_(0x68250000, IICLowReg);
2657 0 : WriteRegister_(0x00000001, IICHighReg);
2658 :
2659 0 : WriteRegister_(0x68260000, IICLowReg);
2660 0 : WriteRegister_(0x00000001, IICHighReg);
2661 :
2662 0 : WriteRegister_(0x68270000, IICLowReg);
2663 0 : WriteRegister_(0x00000001, IICHighReg);
2664 :
2665 0 : WriteRegister_(0x68280000, IICLowReg);
2666 0 : WriteRegister_(0x00000001, IICHighReg);
2667 :
2668 0 : WriteRegister_(0x68290000, IICLowReg);
2669 0 : WriteRegister_(0x00000001, IICHighReg);
2670 :
2671 0 : WriteRegister_(0x682A0000, IICLowReg);
2672 0 : WriteRegister_(0x00000001, IICHighReg);
2673 :
2674 0 : WriteRegister_(0x682B0000, IICLowReg);
2675 0 : WriteRegister_(0x00000001, IICHighReg);
2676 :
2677 0 : WriteRegister_(0x682C0000, IICLowReg);
2678 0 : WriteRegister_(0x00000001, IICHighReg);
2679 :
2680 0 : WriteRegister_(0x682D0000, IICLowReg);
2681 0 : WriteRegister_(0x00000001, IICHighReg);
2682 :
2683 0 : WriteRegister_(0x682E0000, IICLowReg);
2684 0 : WriteRegister_(0x00000001, IICHighReg);
2685 :
2686 0 : WriteRegister_(0x682F0000, IICLowReg);
2687 0 : WriteRegister_(0x00000001, IICHighReg);
2688 :
2689 0 : WriteRegister_(0x68300000, IICLowReg);
2690 0 : WriteRegister_(0x00000001, IICHighReg);
2691 :
2692 0 : WriteRegister_(0x68310000, IICLowReg);
2693 0 : WriteRegister_(0x00000001, IICHighReg);
2694 :
2695 0 : WriteRegister_(0x68320000, IICLowReg);
2696 0 : WriteRegister_(0x00000001, IICHighReg);
2697 :
2698 0 : WriteRegister_(0x68330000, IICLowReg);
2699 0 : WriteRegister_(0x00000001, IICHighReg);
2700 :
2701 0 : WriteRegister_(0x68340000, IICLowReg);
2702 0 : WriteRegister_(0x00000001, IICHighReg);
2703 :
2704 0 : WriteRegister_(0x68350000, IICLowReg);
2705 0 : WriteRegister_(0x00000001, IICHighReg);
2706 :
2707 0 : WriteRegister_(0x68360000, IICLowReg);
2708 0 : WriteRegister_(0x00000001, IICHighReg);
2709 :
2710 0 : WriteRegister_(0x68370000, IICLowReg);
2711 0 : WriteRegister_(0x00000001, IICHighReg);
2712 :
2713 0 : WriteRegister_(0x68380000, IICLowReg);
2714 0 : WriteRegister_(0x00000001, IICHighReg);
2715 :
2716 0 : WriteRegister_(0x68390000, IICLowReg);
2717 0 : WriteRegister_(0x00000001, IICHighReg);
2718 :
2719 0 : WriteRegister_(0x683A0000, IICLowReg);
2720 0 : WriteRegister_(0x00000001, IICHighReg);
2721 :
2722 0 : WriteRegister_(0x683B0000, IICLowReg);
2723 0 : WriteRegister_(0x00000001, IICHighReg);
2724 :
2725 0 : WriteRegister_(0x683C0000, IICLowReg);
2726 0 : WriteRegister_(0x00000001, IICHighReg);
2727 :
2728 0 : WriteRegister_(0x683D0000, IICLowReg);
2729 0 : WriteRegister_(0x00000001, IICHighReg);
2730 :
2731 0 : WriteRegister_(0x683E0000, IICLowReg);
2732 0 : WriteRegister_(0x00000001, IICHighReg);
2733 :
2734 0 : WriteRegister_(0x683F0000, IICLowReg);
2735 0 : WriteRegister_(0x00000001, IICHighReg);
2736 :
2737 0 : WriteRegister_(0x68400000, IICLowReg);
2738 0 : WriteRegister_(0x00000001, IICHighReg);
2739 :
2740 0 : WriteRegister_(0x68410000, IICLowReg);
2741 0 : WriteRegister_(0x00000001, IICHighReg);
2742 :
2743 0 : WriteRegister_(0x68420000, IICLowReg);
2744 0 : WriteRegister_(0x00000001, IICHighReg);
2745 :
2746 0 : WriteRegister_(0x68430000, IICLowReg);
2747 0 : WriteRegister_(0x00000001, IICHighReg);
2748 :
2749 0 : WriteRegister_(0x68440000, IICLowReg);
2750 0 : WriteRegister_(0x00000001, IICHighReg);
2751 :
2752 0 : WriteRegister_(0x68450000, IICLowReg);
2753 0 : WriteRegister_(0x00000001, IICHighReg);
2754 :
2755 0 : WriteRegister_(0x68460000, IICLowReg);
2756 0 : WriteRegister_(0x00000001, IICHighReg);
2757 :
2758 0 : WriteRegister_(0x68470000, IICLowReg);
2759 0 : WriteRegister_(0x00000001, IICHighReg);
2760 :
2761 0 : WriteRegister_(0x68480000, IICLowReg);
2762 0 : WriteRegister_(0x00000001, IICHighReg);
2763 :
2764 0 : WriteRegister_(0x68490000, IICLowReg);
2765 0 : WriteRegister_(0x00000001, IICHighReg);
2766 :
2767 0 : WriteRegister_(0x684A0000, IICLowReg);
2768 0 : WriteRegister_(0x00000001, IICHighReg);
2769 :
2770 0 : WriteRegister_(0x684B0000, IICLowReg);
2771 0 : WriteRegister_(0x00000001, IICHighReg);
2772 :
2773 0 : WriteRegister_(0x684C0000, IICLowReg);
2774 0 : WriteRegister_(0x00000001, IICHighReg);
2775 :
2776 0 : WriteRegister_(0x684D0000, IICLowReg);
2777 0 : WriteRegister_(0x00000001, IICHighReg);
2778 :
2779 0 : WriteRegister_(0x684E0000, IICLowReg);
2780 0 : WriteRegister_(0x00000001, IICHighReg);
2781 :
2782 0 : WriteRegister_(0x684F0000, IICLowReg);
2783 0 : WriteRegister_(0x00000001, IICHighReg);
2784 :
2785 0 : WriteRegister_(0x68500000, IICLowReg);
2786 0 : WriteRegister_(0x00000001, IICHighReg);
2787 :
2788 0 : WriteRegister_(0x68510000, IICLowReg);
2789 0 : WriteRegister_(0x00000001, IICHighReg);
2790 :
2791 0 : WriteRegister_(0x68520000, IICLowReg);
2792 0 : WriteRegister_(0x00000001, IICHighReg);
2793 :
2794 0 : WriteRegister_(0x68530000, IICLowReg);
2795 0 : WriteRegister_(0x00000001, IICHighReg);
2796 :
2797 0 : WriteRegister_(0x68540000, IICLowReg);
2798 0 : WriteRegister_(0x00000001, IICHighReg);
2799 :
2800 0 : WriteRegister_(0x68550000, IICLowReg);
2801 0 : WriteRegister_(0x00000001, IICHighReg);
2802 :
2803 0 : WriteRegister_(0x68560000, IICLowReg);
2804 0 : WriteRegister_(0x00000001, IICHighReg);
2805 :
2806 0 : WriteRegister_(0x68570000, IICLowReg);
2807 0 : WriteRegister_(0x00000001, IICHighReg);
2808 :
2809 0 : WriteRegister_(0x68580000, IICLowReg);
2810 0 : WriteRegister_(0x00000001, IICHighReg);
2811 :
2812 0 : WriteRegister_(0x68590000, IICLowReg);
2813 0 : WriteRegister_(0x00000001, IICHighReg);
2814 :
2815 0 : WriteRegister_(0x685A0000, IICLowReg);
2816 0 : WriteRegister_(0x00000001, IICHighReg);
2817 :
2818 0 : WriteRegister_(0x685B0000, IICLowReg);
2819 0 : WriteRegister_(0x00000001, IICHighReg);
2820 :
2821 0 : WriteRegister_(0x685C0000, IICLowReg);
2822 0 : WriteRegister_(0x00000001, IICHighReg);
2823 :
2824 0 : WriteRegister_(0x685D0000, IICLowReg);
2825 0 : WriteRegister_(0x00000001, IICHighReg);
2826 :
2827 0 : WriteRegister_(0x685E0000, IICLowReg);
2828 0 : WriteRegister_(0x00000001, IICHighReg);
2829 :
2830 0 : WriteRegister_(0x685F0000, IICLowReg);
2831 0 : WriteRegister_(0x00000001, IICHighReg);
2832 :
2833 0 : WriteRegister_(0x68600000, IICLowReg);
2834 0 : WriteRegister_(0x00000001, IICHighReg);
2835 :
2836 0 : WriteRegister_(0x68610000, IICLowReg);
2837 0 : WriteRegister_(0x00000001, IICHighReg);
2838 :
2839 : // set page 9
2840 0 : WriteRegister_(0x68010900, IICLowReg);
2841 0 : WriteRegister_(0x00000001, IICHighReg);
2842 :
2843 : // page 9 registers
2844 0 : WriteRegister_(0x680E0200, IICLowReg);
2845 0 : WriteRegister_(0x00000001, IICHighReg);
2846 :
2847 0 : WriteRegister_(0x68430100, IICLowReg);
2848 0 : WriteRegister_(0x00000001, IICHighReg);
2849 :
2850 0 : WriteRegister_(0x68490F00, IICLowReg);
2851 0 : WriteRegister_(0x00000001, IICHighReg);
2852 :
2853 0 : WriteRegister_(0x684A0F00, IICLowReg);
2854 0 : WriteRegister_(0x00000001, IICHighReg);
2855 :
2856 0 : WriteRegister_(0x684E4900, IICLowReg);
2857 0 : WriteRegister_(0x00000001, IICHighReg);
2858 :
2859 0 : WriteRegister_(0x684F0200, IICLowReg);
2860 0 : WriteRegister_(0x00000001, IICHighReg);
2861 :
2862 0 : WriteRegister_(0x685E0000, IICLowReg);
2863 0 : WriteRegister_(0x00000001, IICHighReg);
2864 :
2865 : // set page A
2866 0 : WriteRegister_(0x68010A00, IICLowReg);
2867 0 : WriteRegister_(0x00000001, IICHighReg);
2868 :
2869 : // page A registers
2870 0 : WriteRegister_(0x68020000, IICLowReg);
2871 0 : WriteRegister_(0x00000001, IICHighReg);
2872 :
2873 0 : WriteRegister_(0x68030100, IICLowReg);
2874 0 : WriteRegister_(0x00000001, IICHighReg);
2875 :
2876 0 : WriteRegister_(0x68040100, IICLowReg);
2877 0 : WriteRegister_(0x00000001, IICHighReg);
2878 :
2879 0 : WriteRegister_(0x68050100, IICLowReg);
2880 0 : WriteRegister_(0x00000001, IICHighReg);
2881 :
2882 0 : WriteRegister_(0x68140000, IICLowReg);
2883 0 : WriteRegister_(0x00000001, IICHighReg);
2884 :
2885 0 : WriteRegister_(0x681A0000, IICLowReg);
2886 0 : WriteRegister_(0x00000001, IICHighReg);
2887 :
2888 : // set page B
2889 0 : WriteRegister_(0x68010B00, IICLowReg);
2890 0 : WriteRegister_(0x00000001, IICHighReg);
2891 :
2892 : // page B registers
2893 0 : WriteRegister_(0x68442F00, IICLowReg);
2894 0 : WriteRegister_(0x00000001, IICHighReg);
2895 :
2896 0 : WriteRegister_(0x68460000, IICLowReg);
2897 0 : WriteRegister_(0x00000001, IICHighReg);
2898 :
2899 0 : WriteRegister_(0x68470000, IICLowReg);
2900 0 : WriteRegister_(0x00000001, IICHighReg);
2901 :
2902 0 : WriteRegister_(0x68480000, IICLowReg);
2903 0 : WriteRegister_(0x00000001, IICHighReg);
2904 :
2905 0 : WriteRegister_(0x684A0200, IICLowReg);
2906 0 : WriteRegister_(0x00000001, IICHighReg);
2907 :
2908 0 : WriteRegister_(0x68570E00, IICLowReg);
2909 0 : WriteRegister_(0x00000001, IICHighReg);
2910 :
2911 0 : WriteRegister_(0x68580100, IICLowReg);
2912 0 : WriteRegister_(0x00000001, IICHighReg);
2913 :
2914 : // End configuration registers
2915 : //
2916 : // Start configuration postamble
2917 : // set page 5
2918 0 : WriteRegister_(0x68010500, IICLowReg);
2919 0 : WriteRegister_(0x00000001, IICHighReg);
2920 :
2921 : // page 5 registers
2922 0 : WriteRegister_(0x68140100, IICLowReg);
2923 0 : WriteRegister_(0x00000001, IICHighReg);
2924 :
2925 : // set page 0
2926 0 : WriteRegister_(0x68010000, IICLowReg);
2927 0 : WriteRegister_(0x00000001, IICHighReg);
2928 :
2929 : // page 0 registers
2930 0 : WriteRegister_(0x681C0100, IICLowReg);
2931 0 : WriteRegister_(0x00000001, IICHighReg);
2932 :
2933 : // set page 5
2934 0 : WriteRegister_(0x68010500, IICLowReg);
2935 0 : WriteRegister_(0x00000001, IICHighReg);
2936 :
2937 : // page 5 registers
2938 0 : WriteRegister_(0x68400000, IICLowReg);
2939 0 : WriteRegister_(0x00000001, IICHighReg);
2940 :
2941 : // set page B
2942 0 : WriteRegister_(0x68010B00, IICLowReg);
2943 0 : WriteRegister_(0x00000001, IICHighReg);
2944 :
2945 : // page B registers
2946 0 : WriteRegister_(0x6824C300, IICLowReg);
2947 0 : WriteRegister_(0x00000001, IICHighReg);
2948 :
2949 0 : WriteRegister_(0x68250200, IICLowReg);
2950 0 : WriteRegister_(0x00000001, IICHighReg);
2951 0 : }
|
