otsdaq-mu2e-stm  5.02.01
stm_data.hh
1 #ifndef STM_DATA_hh
2 #define STM_DATA_hh
3 
4 #include <iterator>
5 #include <cmath>
6 
7 // Hex reader
8 #include "Mu2e-STMDAQ/utils/Hex.hh"
9 // Async Logger code
10 #include "Mu2e-STMDAQ/utils/async_logger.hh"
11 
12 // Config code
13 #include "Mu2e-STMDAQ/config/include/master_config.hh" // master
14 #include "Mu2e-STMDAQ/config/include/fw_config.hh" // firmware
15 #include "Mu2e-STMDAQ/config/include/mu2e_config.hh" // mu2e
16 #include "Mu2e-STMDAQ/config/include/udp_config.hh" // udp
17 #include "Mu2e-STMDAQ/config/include/zs_config.hh" // zero suppression
18 #include "Mu2e-STMDAQ/config/include/prescale_config.hh" // prescale
19 #include "Mu2e-STMDAQ/config/include/write_config.hh" // file writing
20 #include "Mu2e-STMDAQ/config/include/buffer_config.hh" // buffers
21 #include "Mu2e-STMDAQ/config/include/baseline_config.hh" // adc baseline
22 #include "Mu2e-STMDAQ/config/include/mwd_config.hh" // moving window algorithm
23 #include "Mu2e-STMDAQ/config/include/pulseheight_config.hh" // labr pulse-height algorithm
24 #include "Mu2e-STMDAQ/config/include/dqm_config.hh" // dqm
25 #include "Mu2e-STMDAQ/config/include/tcp_config.hh" // tcp
26 
27 // Number of data channels
28 static constexpr int CHNUM = 2;
29 // Signal HPGE data as CHANNEL 0
30 static constexpr int HPGE = 0;
31 // Signal LABR data as CHANNEL 1
32 static constexpr int LABR = 1;
33 
34 // Maxiumum packet size in bytes
35 static constexpr uint16_t MAX_PACKET_SIZE = 8198;
36 // Max length of packet in number of int16_t values
37 static constexpr uint16_t MAX_PACKET_LEN = MAX_PACKET_SIZE/2;
38 
39 // Firmware packet header size in bytes
40 static constexpr uint16_t pHdr_Size = 6;
41 // Firmware packet header length
42 static constexpr uint16_t pHdr_Len = pHdr_Size/2;
43 // Firmware packet header elements
44 static constexpr uint16_t pHdr_pNum1 = 0; // Packet number 2
45 static constexpr uint16_t pHdr_pNum2 = 1; // Packet number 1
46 static constexpr uint16_t pHdr_end = 2; // Packet checksum
47 static constexpr uint16_t pHdr_check = 0xFFEE;
48 
49 // 0xDEADBEEF
50 static constexpr uint16_t DEAD = 0xDEAD;
51 static constexpr uint16_t BEEF = 0xBEEF;
52 
53 // Firmware event header size in bytes
54 static constexpr uint16_t fw_eHdr_size = 64;
55 // Firmware event header length
56 static constexpr uint16_t fw_eHdr_len = fw_eHdr_size/sizeof(int16_t);
57 
58 // Firmware event header elements
59 struct fw_eHdr_info{
60 
61  // Size in bytes of the event header
62  static constexpr uint16_t size = fw_eHdr_size;
63  // Length in int16_t values of the event header
64  static constexpr uint16_t len = fw_eHdr_len;
65 
66  // Size in bytes of the event header anchor
67  static constexpr uint16_t anchor_size = 8;
68  // Length in int16_t values of the header start
69  static constexpr uint16_t anchor_len = anchor_size/2;
70  // Starting index of the header anchor
71  static constexpr uint16_t anchor_start = 0;
72 
73  // Event header anchor data
74  static constexpr int16_t anchor_data[anchor_len]
75  = {static_cast<int16_t>(0xCAFE), // 0 = 0xCAFE
76  static_cast<int16_t>(0xBBBB), // 1 = 0xBBBB
77  static_cast<int16_t>(0xAAAA), // 2 = 0xAAAA
78  static_cast<int16_t>(0xCAFE)}; // 3 = 0xCAFE
79 
80  // Index positions of event header components
81  static constexpr uint16_t anchor_0 = 0; // 0xCAFE
82  static constexpr uint16_t anchor_1 = 1; // 0xBBBB
83  static constexpr uint16_t anchor_2 = 2; // 0xAAAA
84  static constexpr uint16_t anchor_3 = 3; // 0xCAFE
85  static constexpr uint16_t ADCclk_0 = 4; // ADC Clock (75 MHz) 0
86  static constexpr uint16_t ADCclk_1 = 5; // ADC Clock (75 MHz) 1
87  static constexpr uint16_t ADCclk_2 = 6; // ADC Clock (75 MHz) 2
88  static constexpr uint16_t ADCclk_3 = 7; // ADC Clock (75 MHz) 3
89  static constexpr uint16_t EvNum_0 = 8; // Event Number 0
90  static constexpr uint16_t EvNum_1 = 9; // Event Number 1
91  static constexpr uint16_t EvNum_2 = 10; // Event Number 2
92  static constexpr uint16_t EWT_0 = 11; // DTC Event Window Tag 0
93  static constexpr uint16_t EWT_1 = 12; // DTC Event Window Tag 1
94  static constexpr uint16_t EWT_2 = 13; // DTC Event Window Tag 2
95  static constexpr uint16_t EM_0 = 14; // DTC Event Mode 0
96  static constexpr uint16_t EM_1 = 15; // DTC Event Mode 1
97  static constexpr uint16_t EM_2_DRTDC = 16; // DTC Event Mode 2 + Delivery Ring TDC
98  static constexpr uint16_t EvStart = 17; // Event Start Offset
99  static constexpr uint16_t EvInPacket = 18; // Portion of event in packet
100  static constexpr uint16_t Beef = 19; // 0xBEEF
101  static constexpr uint16_t SubRunNum_0 = 20; // Subrun number 1
102  static constexpr uint16_t SubRunNum_1 = 21; // Subrun number 2
103  static constexpr uint16_t ZSflag_PreVal = 22; // ZS flag + prescale value
104  static constexpr uint16_t EvLen = 23; // Total length of event
105  static constexpr uint16_t RunNum_0 = 24; // Run number from DCS write 1
106  static constexpr uint16_t RunNum_1 = 25; // Run number from DCS write 2
107  static constexpr uint16_t RunNum_2 = 26; // Run number from DCS write 3
108  static constexpr uint16_t RunNum_3 = 27; // Run number from DCS write 4
109  static constexpr uint16_t Ch_DTCclk_0 = 28; // Channel [0/1] + DTC Clock (200 MHz) 1
110  static constexpr uint16_t DTCclk_1 = 29; // DTC Clock (200 MHz) 1
111  static constexpr uint16_t DTCclk_2 = 30; // DTC Clock (200 MHz) 2
112  static constexpr uint16_t DTCclk_3 = 31; // DTC Clock (200 MHz) 3
113 
114 };
115 
116 // Static instance of the firmware event header info
117 static constexpr fw_eHdr_info fw_eHdr;
118 
119 // Software event header size in bytes
120 static constexpr uint16_t sw_eHdr_size = 44;
121 // Software event header length
122 static constexpr uint16_t sw_eHdr_len = sw_eHdr_size/sizeof(int16_t);
123 
124 // Software event header elements
125 struct sw_eHdr_info{
126 
127  // Size in bytes of the event header
128  static constexpr uint16_t size = sw_eHdr_size;
129  // Length in int16_t values of the event header
130  static constexpr uint16_t len = sw_eHdr_len;
131 
132  // Software event header anchor
133  static constexpr int16_t anchor = static_cast<int16_t>(0xCAFE);
134 
135  // Index positions of event header components
136  static constexpr uint16_t anchor_start = 0; // 0xCAFE
137  static constexpr uint16_t EWT_0 = 1; // DTC Event Window Tag 0
138  static constexpr uint16_t EWT_1 = 2; // DTC Event Window Tag 1
139  static constexpr uint16_t EWT_2 = 3; // DTC Event Window Tag 2
140  static constexpr uint16_t ADCclk_0 = 4; // ADC Clock (75 MHz) 0
141  static constexpr uint16_t ADCclk_1 = 5; // ADC Clock (75 MHz) 1
142  static constexpr uint16_t ADCclk_2 = 6; // ADC Clock (75 MHz) 2
143  static constexpr uint16_t ADCclk_3 = 7; // ADC Clock (75 MHz) 3
144  static constexpr uint16_t Ch_DTCclk_0 = 8; // Channel [0/1] + DTC Clock (200 MHz) 1
145  static constexpr uint16_t DTCclk_1 = 9; // DTC Clock (200 MHz) 1
146  static constexpr uint16_t DTCclk_2 = 10; // DTC Clock (200 MHz) 2
147  static constexpr uint16_t DTCclk_3 = 11; // DTC Clock (200 MHz) 3
148  static constexpr uint16_t EM_0 = 12; // DTC Event Mode 0
149  static constexpr uint16_t EM_1 = 13; // DTC Event Mode 1
150  static constexpr uint16_t EM_2_DRTDC = 14; // DTC Event Mode 2 + Delivery Ring TDC
151  static constexpr uint16_t PRESCALE = 15; // Raw Prescale On/Off + Raw Prescale Num +
152  // ZS Prescale On/Off + ZS Prescale Num
153  static constexpr uint16_t RAW_LEN = 16; // Raw Data Len
154  static constexpr uint16_t ZS_REGIONS = 17; // Number of ZS data regions
155  static constexpr uint16_t ZS_LEN = 18; // ZS Data Len
156  static constexpr uint16_t PH_NUM = 19; // Number of pulse height values
157  static constexpr uint16_t DATA_FLAGS = 20; // EWT data bad (dropped packets) + EWT missing
158  static constexpr uint16_t anchor_end = 21; // 0xCAFE
159 };
160 
161 // Static instance of the software event header info
162 static constexpr sw_eHdr_info sw_eHdr;
163 
164 // Define software event header type
165 using sw_event_header = std::array<int16_t, sw_eHdr_info::len>;
166 
167 class STMdata{
168 
169 private:
170 
171  // Store reference to the Config instance
172  Config& cfg;
173 
174  // Async Logger
175  const std::shared_ptr<AsyncLogger> logger;
176 
177 public:
178 
179  // Constructor
180  STMdata(Config& cfg,
181  const std::shared_ptr<AsyncLogger>& logger_);
182 
183  // Destructor
184  ~STMdata() {
185  std::cout << "STMdata destructor called.\n";
186  }
187 
188  // Form uint32_t out of 2 x int16_t
189  uint32_t make_uint32_t(int16_t p0, int16_t p1);
190 
191  // Form uint64_t out of 4 x int16_t
192  uint64_t make_uint64_t(int16_t p0, int16_t p1, int16_t p2, int16_t p3);
193 
194  // Split uin32_t into 2 x int16_t
195  std::vector<int16_t> split_uint32_t(uint32_t value);
196 
197  // Split uin64_t into 4 x int16_t
198  std::vector<int16_t> split_uint64_t(uint64_t value);
199 
200  // Get just the event number from the event header
201  uint64_t get_event_number(int16_t* data, uint64_t hdr_index);
202 
203  // Get just the ADC clock time from the event header
204  uint64_t get_ADCclock(int16_t* data, uint64_t hdr_index);
205 
206  // Get just the EWT from the event header
207  uint64_t get_EWT(int16_t* data, uint64_t hdr_index);
208 
209  // Get the event mode
210  uint64_t get_event_mode(int16_t* data, uint64_t hdr_index);
211 
212  // Get the channel number and DTC clock word from the event header
213  uint64_t get_Ch_DTCclk(int16_t* data, uint64_t hdr_index);
214 
215  // Get just the channel number from the event header
216  uint16_t get_channel(int16_t* data, uint64_t hdr_index);
217 
218  // Get just the DTC clock time from the event header
219  uint64_t get_DTCclock(int16_t* data, uint64_t hdr_index);
220 
221  // Check the end of a packet for repeated 0xDEADBEEF
222  uint16_t check_dead_beef(int16_t* data, uint64_t packet_start, uint16_t leftInPacket);
223 
224  // Create software event header from buffer
225  sw_event_header create_sw_eHdr(int16_t* data, uint64_t hdr_index);
226 
227  // Create software event header from individual inputs
228  sw_event_header create_sw_eHdr(uint64_t EWT,
229  uint64_t ADCclk,
230  uint64_t Ch_DTCclk,
231  uint64_t EM);
232 
233  // STMDAQ master config
234  const master_info master_config;
235 
236  // Firmware configuration
237  const fw_info fw_config;
238 
239  // Mu2e configuration
240  const mu2e_info mu2e_config;
241 
242  // UDP configuration
243  const udp_info udp_config;
244 
245  // Zero suppression configuration
246  const zs_info zs_config;
247 
248  // Prescale configuration
249  const prescale_info prescale_config;
250 
251  // MWD configuration
252  const write_info write_config;
253 
254  // Buffer configuration
255  const buffer_info buffer_config;
256 
257  // ADC baseline configuration
258  const baseline_info baseline_config;
259 
260  // MWD configuration
261  const mwd_info mwd_config;
262 
263  // Pulse height configuration
264  const pulseheight_info pulseheight_config;
265 
266  // TCP configuration
267  const tcp_cfg_info tcp_config;
268 
269  // DQM configuration
270  const dqm_info dqm_config;
271 
272 };
273 
274 #endif
Config
Definition: config.hh:19
data
Definition: data.hh:4
baseline_info
Definition: baseline_config.hh:13
buffer_info
Definition: buffer_config.hh:9
dqm_info
Definition: dqm_config.hh:11
fw_eHdr_info
Definition: stm_data.hh:59
fw_info
Definition: fw_config.hh:80
master_info
Definition: master_config.hh:10
mu2e_info
Definition: mu2e_config.hh:9
mwd_info
Definition: mwd_config.hh:9
prescale_info
Definition: prescale_config.hh:30
pulseheight_info
Definition: pulseheight_config.hh:9
sw_eHdr_info
Definition: stm_data.hh:125
tcp_cfg_info
Definition: tcp_config.hh:9
udp_info
Definition: udp_config.hh:9
write_info
Definition: write_config.hh:11
zs_info
Definition: zs_config.hh:10